As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects
have become the dominant contributor to circuit delay and a significant component of
power consumption. In order to reduce the length of these interconnects, 3D integration
and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.
3D SICs not only have the potential to reduce average interconnect length and alleviate
many of the problems caused by long global interconnects, but they can offer greater design
flexibility over 2D ICs, significant reductions in power consumption and footprint in
an era of mobile applications, increased on-chip data bandwidth through delay reduction,
and improved heterogeneous integration.
Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.
Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a
die stack, are a source of additional and unique defects not seen before in ICs. At the same
time, testing these TSVs, especially before die stacking, is recognized as a major challenge.
The testing of a 3D stack is constrained by limited test access, test pin availability,
power, and thermal constraints. Therefore, efficient and optimized test architectures are
needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively
expensive.
Methods of testing TSVs prior to bonding continue to be a difficult problem due to test
access and testability issues. Although some built-in self-test (BIST) techniques have been
proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through
TSV probing. This has the benefit of not needing large analog test components on the die,
which is a significant drawback of many BIST architectures. Coupled with an optimization
method described in this dissertation to create parallel test groups for TSVs, test time for
pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is
expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and
structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.
The addition of boundary registers on functional TSV paths required for pre-bond
probing results in an increase in delay on inter-die functional paths. This cost of test
architecture insertion can be a significant drawback, especially considering that one benefit
of 3D integration is that critical paths can be partitioned between dies to reduce their delay.
This dissertation derives a retiming flow that is used to recover the additional delay added
to TSV paths by test cell insertion.
Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary
during 3D-SIC manufacturing. To reduce test cost, the test architecture and test
scheduling for the stack must be optimized to reduce test time across all necessary test
insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm
dies, and soft dies, that give varying degrees of control over 2D test architectures on each
die while optimizing the 3D test architecture. Integer linear programming models are developed
to provide an optimal 3D test architecture and test schedule for the dies in the 3D
stack considering any or all post-bond test insertions. Results show that the ILP models
outperform other optimization methods across a range of 3D benchmark circuits.
In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.
The proposed techniques enable pre-bond TSV and structural test while maintaining a
relatively low test cost. Future work will continue to enable testing of 3D SICs to move
industry closer to realizing the true potential of 3D integration.
","abstract_html":"<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.</p><p>3D SICs not only have the potential to reduce average interconnect length and alleviate</p><p>many of the problems caused by long global interconnects, but they can offer greater design</p><p>flexibility over 2D ICs, significant reductions in power consumption and footprint in</p><p>an era of mobile applications, increased on-chip data bandwidth through delay reduction,</p><p>and improved heterogeneous integration.</p><p>Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.</p><p>Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a</p><p>die stack, are a source of additional and unique defects not seen before in ICs. At the same</p><p>time, testing these TSVs, especially before die stacking, is recognized as a major challenge.</p><p>The testing of a 3D stack is constrained by limited test access, test pin availability,</p><p>power, and thermal constraints. Therefore, efficient and optimized test architectures are</p><p>needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively</p><p>expensive.</p><p>Methods of testing TSVs prior to bonding continue to be a difficult problem due to test</p><p>access and testability issues. Although some built-in self-test (BIST) techniques have been</p><p>proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through</p><p>TSV probing. This has the benefit of not needing large analog test components on the die,</p><p>which is a significant drawback of many BIST architectures. Coupled with an optimization</p><p>method described in this dissertation to create parallel test groups for TSVs, test time for</p><p>pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is</p><p>expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and</p><p>structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.</p><p>The addition of boundary registers on functional TSV paths required for pre-bond</p><p>probing results in an increase in delay on inter-die functional paths. This cost of test</p><p>architecture insertion can be a significant drawback, especially considering that one benefit</p><p>of 3D integration is that critical paths can be partitioned between dies to reduce their delay.</p><p>This dissertation derives a retiming flow that is used to recover the additional delay added</p><p>to TSV paths by test cell insertion.</p><p>Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary</p><p>during 3D-SIC manufacturing. To reduce test cost, the test architecture and test</p><p>scheduling for the stack must be optimized to reduce test time across all necessary test</p><p>insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm</p><p>dies, and soft dies, that give varying degrees of control over 2D test architectures on each</p><p>die while optimizing the 3D test architecture. Integer linear programming models are developed</p><p>to provide an optimal 3D test architecture and test schedule for the dies in the 3D</p><p>stack considering any or all post-bond test insertions. Results show that the ILP models</p><p>outperform other optimization methods across a range of 3D benchmark circuits.</p><p>In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.</p><p>The proposed techniques enable pre-bond TSV and structural test while maintaining a</p><p>relatively low test cost. Future work will continue to enable testing of 3D SICs to move</p><p>industry closer to realizing the true potential of 3D integration.</p>","abstract_has_math":false,"creators":["Noia, Brandon Robert"],"institution":null,"degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["Chakrabarty, Krishnendu"],"committee_chairs":[],"committee_members":[],"year":2014,"date_issued":"2014","date_published":"2014","updated_at":"2026-07-24T02:06:57Z","subjects":["Electrical engineering","Computer engineering","3D SIC","DFT","TSV"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10161/8666","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Chakrabarty, Krishnendu"]},{"key":"dc:creator","label":"Author","values":["Noia, Brandon Robert"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2014-05-14T19:16:48Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2014-05-14T19:16:48Z"]},{"key":"dc:date.issued","label":"Date","values":["2014"]},{"key":"dc:type","label":"Dc Type","values":["Dissertation"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Electrical engineering","Computer engineering","3D SIC","DFT","TSV"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10161/8666"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects
have become the dominant contributor to circuit delay and a significant component of
power consumption. In order to reduce the length of these interconnects, 3D integration
and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.
3D SICs not only have the potential to reduce average interconnect length and alleviate
many of the problems caused by long global interconnects, but they can offer greater design
flexibility over 2D ICs, significant reductions in power consumption and footprint in
an era of mobile applications, increased on-chip data bandwidth through delay reduction,
and improved heterogeneous integration.
Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.
Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a
die stack, are a source of additional and unique defects not seen before in ICs. At the same
time, testing these TSVs, especially before die stacking, is recognized as a major challenge.
The testing of a 3D stack is constrained by limited test access, test pin availability,
power, and thermal constraints. Therefore, efficient and optimized test architectures are
needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively
expensive.
Methods of testing TSVs prior to bonding continue to be a difficult problem due to test
access and testability issues. Although some built-in self-test (BIST) techniques have been
proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through
TSV probing. This has the benefit of not needing large analog test components on the die,
which is a significant drawback of many BIST architectures. Coupled with an optimization
method described in this dissertation to create parallel test groups for TSVs, test time for
pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is
expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and
structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.
The addition of boundary registers on functional TSV paths required for pre-bond
probing results in an increase in delay on inter-die functional paths. This cost of test
architecture insertion can be a significant drawback, especially considering that one benefit
of 3D integration is that critical paths can be partitioned between dies to reduce their delay.
This dissertation derives a retiming flow that is used to recover the additional delay added
to TSV paths by test cell insertion.
Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary
during 3D-SIC manufacturing. To reduce test cost, the test architecture and test
scheduling for the stack must be optimized to reduce test time across all necessary test
insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm
dies, and soft dies, that give varying degrees of control over 2D test architectures on each
die while optimizing the 3D test architecture. Integer linear programming models are developed
to provide an optimal 3D test architecture and test schedule for the dies in the 3D
stack considering any or all post-bond test insertions. Results show that the ILP models
outperform other optimization methods across a range of 3D benchmark circuits.
In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.
The proposed techniques enable pre-bond TSV and structural test while maintaining a
relatively low test cost. Future work will continue to enable testing of 3D SICs to move
industry closer to realizing the true potential of 3D integration.
"]},{"key":"dc:title","label":"Title","values":["Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs"]}]}],"canonical_facts":{"dc:contributor.advisor":["Chakrabarty, Krishnendu"],"dc:creator":["Noia, Brandon Robert"],"dc:date.accessioned":["2014-05-14T19:16:48Z"],"dc:date.available":["2014-05-14T19:16:48Z"],"dc:date.issued":["2014"],"dc:description.abstract":["As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects
have become the dominant contributor to circuit delay and a significant component of
power consumption. In order to reduce the length of these interconnects, 3D integration
and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry.
3D SICs not only have the potential to reduce average interconnect length and alleviate
many of the problems caused by long global interconnects, but they can offer greater design
flexibility over 2D ICs, significant reductions in power consumption and footprint in
an era of mobile applications, increased on-chip data bandwidth through delay reduction,
and improved heterogeneous integration.
Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.
Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a
die stack, are a source of additional and unique defects not seen before in ICs. At the same
time, testing these TSVs, especially before die stacking, is recognized as a major challenge.
The testing of a 3D stack is constrained by limited test access, test pin availability,
power, and thermal constraints. Therefore, efficient and optimized test architectures are
needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively
expensive.
Methods of testing TSVs prior to bonding continue to be a difficult problem due to test
access and testability issues. Although some built-in self-test (BIST) techniques have been
proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through
TSV probing. This has the benefit of not needing large analog test components on the die,
which is a significant drawback of many BIST architectures. Coupled with an optimization
method described in this dissertation to create parallel test groups for TSVs, test time for
pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is
expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and
structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.
The addition of boundary registers on functional TSV paths required for pre-bond
probing results in an increase in delay on inter-die functional paths. This cost of test
architecture insertion can be a significant drawback, especially considering that one benefit
of 3D integration is that critical paths can be partitioned between dies to reduce their delay.
This dissertation derives a retiming flow that is used to recover the additional delay added
to TSV paths by test cell insertion.
Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary
during 3D-SIC manufacturing. To reduce test cost, the test architecture and test
scheduling for the stack must be optimized to reduce test time across all necessary test
insertions. This dissertation examines three paradigms for 3D integration - hard dies, firm
dies, and soft dies, that give varying degrees of control over 2D test architectures on each
die while optimizing the 3D test architecture. Integer linear programming models are developed
to provide an optimal 3D test architecture and test schedule for the dies in the 3D
stack considering any or all post-bond test insertions. Results show that the ILP models
outperform other optimization methods across a range of 3D benchmark circuits.
In summary, this dissertation targets testing and design-for-test (DFT) of 3D SICs.
The proposed techniques enable pre-bond TSV and structural test while maintaining a
relatively low test cost. Future work will continue to enable testing of 3D SICs to move
industry closer to realizing the true potential of 3D integration.
"],"dc:identifier.uri":["https://hdl.handle.net/10161/8666"],"dc:subject":["Electrical engineering","Computer engineering","3D SIC","DFT","TSV"],"dc:title":["Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs"],"dc:type":["Dissertation"]},"updated_at":"2026-07-24T02:06:57Z"}