{"id":{"repo_id":"de-montfort","oai_identifier":"oai:dora.dmu.ac.uk:2086/25701"},"canonical_url":"https://search.dev.ndltd.org/etd/de-montfort/oai:dora.dmu.ac.uk:2086/25701","repository":{"repo_id":"de-montfort","name":"De Montfort University","base_url":"https://dora.dmu.ac.uk/server/oai/request"},"display":{"title":"The Clustered Insulated Gate Bipolar Transistor (CIGBT) — from concept to manufacturing","abstract":"In this thesis the novel power device called Clustered Insulated Gate Bipolar Transistor (CIGBT) is developed from concept to a pre-manufacturing product. The CIGBT uses MOS gate control over a thyristor action to achieve low conduction losses. A “Capacitive” turn-on mechanism ensures a smooth turn on of the device without any snap back in the IV characteristics. An embedded self clamping” feature ensures protection of the gate and cathode structures from high anode voltages, which results in excellent current saturation and efficient switching performance. Principals of the device operation and the internal mechanisms at different operation conditions have been analysed using numerical modeUing. It is shown that a superior trade off between the on state voltage and the turn off losses is achieved by CIGBT in comparison IGBT. Two fabrication processes have been developed during the study. The first one is based on a standard CMOS process and offers low voltage CMOS compatibility for monolithic integration. 'Phis process was successfully used to prove the CIGBT concept in silicon. The second fabrication process has been developed with a manufacturing of the single CIGBT device in mind. It was designed to overcome the limitation of the first process and produce optimum CIGBT devices. Influence of the process variation on the device performance and the stability of the process have been analysed using numerical modelling and measured results from process test structures. It was found that a tight control of the implantation dose for P well and N well is required to ensure it is within 5% of the optimum value. The development was also focused on the planar devices with a 1700 V breakdown voltage built in Non Punch Through technology. Using improved fabrication process, CIGBT devices with different layout options have been produced. These devices have been analysed electrically in order to find the optimum design layout. All devices tested showed excellent on state and switching behaviour and withstood a short circuit condition for 10 psec. It was found that a square cell layout is preferred to stripe and the optimum cathode cell spacing lies between 10 and 12 pm. It was concluded that the best layout for the CIGBT is 8x8 square design with a 12 pm cathode cell spacing. Measured results of the planar 25 mm^ 1700 V NPT CIGBT devices showed an average forward voltage drop of 2.39V at 25 A, and turn off losses of 6.63 mJ at 25A, 900V. The trade off achieved by these devices is superior to that for commercial planar NPT IGBTs. In fact it is among the lowest values reported for IGBT using more advanced trench and field stop technologies.","abstract_html":"In this thesis the novel power device called Clustered Insulated Gate Bipolar Transistor (CIGBT) is developed from concept to a pre-manufacturing product. The CIGBT uses MOS gate control over a thyristor action to achieve low conduction losses. A “Capacitive” turn-on mechanism ensures a smooth turn on of the device without any snap back in the IV characteristics. An embedded self clamping” feature ensures protection of the gate and cathode structures from high anode voltages, which results in excellent current saturation and efficient switching performance. Principals of the device operation and the internal mechanisms at different operation conditions have been analysed using numerical modeUing. It is shown that a superior trade off between the on state voltage and the turn off losses is achieved by CIGBT in comparison IGBT. Two fabrication processes have been developed during the study. The first one is based on a standard CMOS process and offers low voltage CMOS compatibility for monolithic integration. &#x27;Phis process was successfully used to prove the CIGBT concept in silicon. The second fabrication process has been developed with a manufacturing of the single CIGBT device in mind. It was designed to overcome the limitation of the first process and produce optimum CIGBT devices. Influence of the process variation on the device performance and the stability of the process have been analysed using numerical modelling and measured results from process test structures. It was found that a tight control of the implantation dose for P well and N well is required to ensure it is within 5% of the optimum value. The development was also focused on the planar devices with a 1700 V breakdown voltage built in Non Punch Through technology. Using improved fabrication process, CIGBT devices with different layout options have been produced. These devices have been analysed electrically in order to find the optimum design layout. All devices tested showed excellent on state and switching behaviour and withstood a short circuit condition for 10 psec. It was found that a square cell layout is preferred to stripe and the optimum cathode cell spacing lies between 10 and 12 pm. It was concluded that the best layout for the CIGBT is 8x8 square design with a 12 pm cathode cell spacing. Measured results of the planar 25 mm^ 1700 V NPT CIGBT devices showed an average forward voltage drop of 2.39V at 25 A, and turn off losses of 6.63 mJ at 25A, 900V. The trade off achieved by these devices is superior to that for commercial planar NPT IGBTs. In fact it is among the lowest values reported for IGBT using more advanced trench and field stop technologies.","abstract_has_math":false,"creators":["Vershinin, Konstantin"],"institution":"De Montfort University","degree_name":"PhD","degree_level":"Doctoral","degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2006,"date_issued":"2006-05","date_published":"2006-05","updated_at":"2026-07-24T06:18:33Z","subjects":[],"languages":[],"rights":[],"rights_urls":["https://dora.dmu.ac.uk/bitstreams/cdd914e4-2801-429a-adf8-7641961bc929/download"],"identifier_entries":[]},"links":{"outbound_url":null,"outbound_label":null,"outbound_source":null},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Vershinin, Konstantin"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.issued","label":"Date","values":["2006-05"]},{"key":"dc:publisher.department","label":"Dc Publisher Department","values":["Faculty of Technology, Arts and Culture"]},{"key":"dc:publisher.institution","label":"Dc Publisher Institution","values":["De Montfort University"]},{"key":"dc:relation.isreferencedby","label":"Dc Relation Isreferencedby","values":["https://hdl.handle.net/2086/25701"]},{"key":"dc:type","label":"Dc Type","values":["Thesis or dissertation"]},{"key":"dc:type.qualificationlevel","label":"Dc Type Qualificationlevel","values":["Doctoral"]},{"key":"dc:type.qualificationname","label":"Dc Type Qualificationname","values":["PhD"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:rights","label":"Dc Rights","values":["https://dora.dmu.ac.uk/bitstreams/cdd914e4-2801-429a-adf8-7641961bc929/download"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://dora.dmu.ac.uk/bitstreams/ddae7331-a3f5-40fd-b92d-7c811ee51b05/download"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["In this thesis the novel power device called Clustered Insulated Gate Bipolar Transistor (CIGBT) is developed from concept to a pre-manufacturing product. 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The second fabrication process has been developed with a manufacturing of the single CIGBT device in mind. It was designed to overcome the limitation of the first process and produce optimum CIGBT devices. Influence of the process variation on the device performance and the stability of the process have been analysed using numerical modelling and measured results from process test structures. It was found that a tight control of the implantation dose for P well and N well is required to ensure it is within 5% of the optimum value. The development was also focused on the planar devices with a 1700 V breakdown voltage built in Non Punch Through technology. Using improved fabrication process, CIGBT devices with different layout options have been produced. These devices have been analysed electrically in order to find the optimum design layout. All devices tested showed excellent on state and switching behaviour and withstood a short circuit condition for 10 psec. It was found that a square cell layout is preferred to stripe and the optimum cathode cell spacing lies between 10 and 12 pm. It was concluded that the best layout for the CIGBT is 8x8 square design with a 12 pm cathode cell spacing. Measured results of the planar 25 mm^ 1700 V NPT CIGBT devices showed an average forward voltage drop of 2.39V at 25 A, and turn off losses of 6.63 mJ at 25A, 900V. The trade off achieved by these devices is superior to that for commercial planar NPT IGBTs. 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Influence of the process variation on the device performance and the stability of the process have been analysed using numerical modelling and measured results from process test structures. It was found that a tight control of the implantation dose for P well and N well is required to ensure it is within 5% of the optimum value. The development was also focused on the planar devices with a 1700 V breakdown voltage built in Non Punch Through technology. Using improved fabrication process, CIGBT devices with different layout options have been produced. These devices have been analysed electrically in order to find the optimum design layout. All devices tested showed excellent on state and switching behaviour and withstood a short circuit condition for 10 psec. It was found that a square cell layout is preferred to stripe and the optimum cathode cell spacing lies between 10 and 12 pm. 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