LATERAL POWER DEVICES AND TECHNOLOGIES FOR HIGH VOLTAGE INTEGRATED CIRCUITS

The prime objective of a High Voltage Power Integrated Circuit (HVPIC) is to integrate high power and low power devices on the same wafer. Such a Power Integrated Circuit (PIC) benefits in cost, weight, functionality and reliability. A Lateral MOS controlled Power Device is a key component in such a monolithic integrated circuit, can handle high voltages, high currents, or a combination of both, with a low on-state resistance and fast switching capability. In addition, isolation technology is essential to realise PIC. this dissertation is devoted to investigate novel lateral power devices and new isolation technologies using extensive numerical simulations and experiments. The performance of Junction Isolated (JI) Lateral Insulated Gate Bipolar Transistor (LIGBT) with a Variation in Lateral Doping (VLD) drift region is investigated using simulations and measurements. The results show significant advancements in breakdown voltages and latch up current densities without compromising forward voltage drop and turn-off losses, furthermore, it is found that a VLD drift region can achieve the required breakdown voltage with smaller drift region lengths in comparison to uniform drift region and use of VLD drift region also benefits to enhance the Safe Operating Area (SOA). A Lateral Double-diffused MOSI’ET (LDMOS) in a novel SOI technology based on alternative high-k dielectrics a.s buried insulators is investigated using numerical simulations. Since the drift region doping is directly proportional to the value of buried insulator's dielectric constant, use of higher k value dielectrics reduce the on-state resistance. In addition, their better thermal conductivity than silicon oxide reduces the problems of self-heating considerably. However, due to increment in output capacitance of the device, switching losses increase with increase in k-value. Partial-Silicon On Insulator (PSOl) technology is a potential alternative to alleviate self-heating issue without loosing the benefits provided by SOI technology. A novel doping profile is proposed to realise high breakdown voltages in ultra-thin Partial SOI (PSOI) technology. Simulation results have shown that PSOl devices achieve higher breakdown voltage and reduced self-heating problem in comparison with SOI devices. However, the on-state resistance is slightly higher than VIJ) SOI due to lesser doping in the drift region. PSOl LDMOS benefits from higher breakdown voltage, in excess of 15OOV. compared to VLD SOI. A new power device structure to enhance the current carrying capability of devices by incorporating additional MOS cathode cells at the bottom of the substrate in LIGBT is investigated in JI technology. It is demonstrated through the device simulations that these cathode cells contribute additional current in the on-state and enhance the conductivity modulation. Consequently, the forward drop of the device is much lower than the conventional LIGBT. Moreover, in the off-state the device blocks voltage similar to lateral RESURF device. In addition, simulations show a significant improvement in forward Bias Safe Operating Area (I'BSOA) while maintaining the similar breakdown voltage, turn-off time and turn-off losses in comparison with conventional LIGBT.

Name dc:type.qualificationname

PhD

Level dc:type.qualificationlevel

Doctoral

Grantor dc:publisher.institution

De Montfort University

Year dc:date.issued

2006

Author dc:creator

• Tadikonda, Ramakrishna

Licence

• https://dora.dmu.ac.uk/bitstreams/460e9d3b-55ce-49c9-89e3-5b59229c8c81/download