From TPU to QPU: Bridging Fidelity Gaps Across Next-Generation Computing Systems
type: CreativeWork
description: Modern computing systems continue to advance rapidly, enabling unprecedented computational capabilities across diverse domains. Among these powerful architectures are AI accelerators such as Tensor Processing Units (TPUs) and quantum computing systems utilizing Quantum Processing Units (QPUs) stand out as trans-formative technologies. Despite their potential, these systems share significant challenges related to hardware infidelity, manifested as error-induced degradation in computational accuracy and reliability. This thesis explicitly addresses cost-effective methods to screen-out defective AI accelerators across next-generation computing architectures and boost quantum circuit output fidelity through hierarchical circuit optimization using advanced machine learning methodologies. This thesis first proposes a cost-eﬀective testing methodology of AI accelerator chips to minimize yield loss. This methodology utilizes detailed circuit-level fault models, exposing how hardware defects propagate to application-level outputs. The approach establishes structured fault characterization that improves application-level robustness without excessive hardware redundancy. Building on insights from classical accelerator fault modeling, the thesis next addresses the analogous issue of fidelity in quantum computing. This work tackles the practical realization of quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices, which are substantially impeded by quantum hardware noise. The computational cost of compiling and re-synthesizing such large circuits grows exponentially with increased qubit count, typically more than 100 qubits, and increased circuit depth, rendering brute-force optimization infeasible, thus, severely reducing circuit fidelity. To mitigate the hardware noise challenge on the output fidelity, we propose a novel quantum circuit partitioning framework based on reinforcement learning (RL) methodologies combined with Graph Neural Networks (GNNs) designed …
abstract: Modern computing systems continue to advance rapidly, enabling unprecedented computational capabilities across diverse domains. Among these powerful architectures are AI accelerators such as Tensor Processing Units (TPUs) and quantum computing systems utilizing Quantum Processing Units (QPUs) stand out as trans-formative technologies. Despite their potential, these systems share significant challenges related to hardware infidelity, manifested as error-induced degradation in computational accuracy and reliability. This thesis explicitly addresses cost-effective methods to screen-out defective AI accelerators across next-generation computing architectures and boost quantum circuit output fidelity through hierarchical circuit optimization using advanced machine learning methodologies. This thesis first proposes a cost-eﬀective testing methodology of AI accelerator chips to minimize yield loss. This methodology utilizes detailed circuit-level fault models, exposing how hardware defects propagate to application-level outputs. The approach establishes structured fault characterization that improves application-level robustness without excessive hardware redundancy. Building on insights from classical accelerator fault modeling, the thesis next addresses the analogous issue of fidelity in quantum computing. This work tackles the practical realization of quantum algorithms on Noisy Intermediate-Scale Quantum (NISQ) devices, which are substantially impeded by quantum hardware noise. The computational cost of compiling and re-synthesizing such large circuits grows exponentially with increased qubit count, typically more than 100 qubits, and increased circuit depth, rendering brute-force optimization infeasible, thus, severely reducing circuit fidelity. To mitigate the hardware noise challenge on the output fidelity, we propose a novel quantum circuit partitioning framework based on reinforcement learning (RL) methodologies combined with Graph Neural Networks (GNNs) designed …
author: Charrwi, Mohammad Walid M
keywords: Noisy Intermediate-Scale Quantum (NISQ), Quantum circuit partitioning, Reinforcement Learning, Systolic array, AI accelerators, VLSI and Circuits, Embedded and Hardware Systems
date published: 2025-01-01T08:00:00Z
date modified: 2026-07-24T01:58:13Z
provider: City University of New York - City College
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: City University of New York - City College