{"id":{"repo_id":"cork","oai_identifier":"oai:cora.ucc.ie:10468/5349"},"canonical_url":"https://search.dev.ndltd.org/etd/cork/oai:cora.ucc.ie:10468/5349","repository":{"repo_id":"cork","name":"University College Cork","base_url":"https://cora.ucc.ie/server/oai/request"},"display":{"title":"An investigation of border traps and interface states in high-k/InGaAs metal-oxide-semiconductor systems","abstract":"One approach to saving energy in metal-oxide-semiconductor field effect transistors (MOSFETs) is to replace SiO2/Si structure with high dielectric constant (high-k) oxides on high mobility channel materials (e.g. InGaAs), which have the potential to achieve a comparable on current and operating frequency to silicon, but at a reduced supply voltage. In this thesis, investigation into border traps (or charge trapping) and interface states, both of which can induce device instability, in HfO2/InGaAs and Al2O3/InGaAs metal-oxidesemiconductor (MOS) structures was carried out with an emphasis on the characterization of border traps using capacitance-voltage (C-V) hysteresis measurement. The charge trapping is observed to be mainly a reversible process. The trapped charge is predominantly localized as a sheet charge near/at the high-k/InGaAs interfacial layer (~1nm), which can contain native oxides of InGaAs. The engineering of the high-k/InGaAs interface is therefore the key to reducing C-V hysteresis and improving device reliability. This work demonstrates the ability to reduce border trap density with forming gas annealing (5% H2 / 95% N2) in the range 3500C~4500C for Al2O3/InGaAs and HfO2/InGaAs MOS structures. Moreover, it is observed that C-V hysteresis increases with a power law dependence with the increasing stress time (in accumulation) at the initial stage of stressing and tends to reach a plateau at sufficiently long stress times due to the filling of almost all the pre-existing border traps. This therefore provides a method to estimate the total trap density under certain oxide field. Furthermore, a combined C-V and hard x-ray photoelectron spectroscopy (HAXPES) study was performed on Al2O3/InGaAs MOS structure, revealing a partially pinned Al2O3/InGaAs interface. The Fermi level position at zero gate bias was calculated using both techniques, and a reasonable agreement was achieved. This combined study thus provides more certainty on the interface state profile extractions.","abstract_html":"One approach to saving energy in metal-oxide-semiconductor field effect transistors (MOSFETs) is to replace SiO2/Si structure with high dielectric constant (high-k) oxides on high mobility channel materials (e.g. InGaAs), which have the potential to achieve a comparable on current and operating frequency to silicon, but at a reduced supply voltage. In this thesis, investigation into border traps (or charge trapping) and interface states, both of which can induce device instability, in HfO2/InGaAs and Al2O3/InGaAs metal-oxidesemiconductor (MOS) structures was carried out with an emphasis on the characterization of border traps using capacitance-voltage (C-V) hysteresis measurement. The charge trapping is observed to be mainly a reversible process. The trapped charge is predominantly localized as a sheet charge near/at the high-k/InGaAs interfacial layer (~1nm), which can contain native oxides of InGaAs. The engineering of the high-k/InGaAs interface is therefore the key to reducing C-V hysteresis and improving device reliability. This work demonstrates the ability to reduce border trap density with forming gas annealing (5% H2 / 95% N2) in the range 3500C~4500C for Al2O3/InGaAs and HfO2/InGaAs MOS structures. Moreover, it is observed that C-V hysteresis increases with a power law dependence with the increasing stress time (in accumulation) at the initial stage of stressing and tends to reach a plateau at sufficiently long stress times due to the filling of almost all the pre-existing border traps. This therefore provides a method to estimate the total trap density under certain oxide field. Furthermore, a combined C-V and hard x-ray photoelectron spectroscopy (HAXPES) study was performed on Al2O3/InGaAs MOS structure, revealing a partially pinned Al2O3/InGaAs interface. The Fermi level position at zero gate bias was calculated using both techniques, and a reasonable agreement was achieved. This combined study thus provides more certainty on the interface state profile extractions.","abstract_has_math":false,"creators":["Lin, Jun"],"institution":"University College Cork","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":["Hurley, Paul K.","Monaghan, Scott"],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017","date_published":"2017","updated_at":"2026-07-24T01:47:55Z","subjects":["InGaAs MOS","Border traps","Interface states"],"languages":["en"],"rights":["© 2017, Jun Lin."],"rights_urls":["http://creativecommons.org/licenses/by-nc-nd/3.0/"],"identifier_entries":[]},"links":{"outbound_url":"https://hdl.handle.net/10468/5349","outbound_label":"Handle","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor.advisor","label":"Advisor","values":["Hurley, Paul K.","Monaghan, Scott"]},{"key":"dc:creator","label":"Author","values":["Lin, Jun"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2018-01-30T12:47:49Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2018-01-30T12:47:49Z"]},{"key":"dc:date.issued","label":"Date","values":["2017"]},{"key":"dc:publisher","label":"Institution","values":["University College Cork"]},{"key":"dc:type","label":"Dc Type","values":["Doctoral thesis"]},{"key":"dc:type.qualificationlevel","label":"Dc Type Qualificationlevel","values":["Doctoral"]},{"key":"dc:type.qualificationname","label":"Dc Type Qualificationname","values":["PhD (Science)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["InGaAs MOS","Border traps","Interface states"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]},{"key":"dc:rights","label":"Dc Rights","values":["© 2017, Jun Lin."]},{"key":"dc:rights.uri","label":"Rights URI","values":["http://creativecommons.org/licenses/by-nc-nd/3.0/"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://hdl.handle.net/10468/5349"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["One approach to saving energy in metal-oxide-semiconductor field effect transistors (MOSFETs) is to replace SiO2/Si structure with high dielectric constant (high-k) oxides on high mobility channel materials (e.g. InGaAs), which have the potential to achieve a comparable on current and operating frequency to silicon, but at a reduced supply voltage. In this thesis, investigation into border traps (or charge trapping) and interface states, both of which can induce device instability, in HfO2/InGaAs and Al2O3/InGaAs metal-oxidesemiconductor (MOS) structures was carried out with an emphasis on the characterization of border traps using capacitance-voltage (C-V) hysteresis measurement. The charge trapping is observed to be mainly a reversible process. The trapped charge is predominantly localized as a sheet charge near/at the high-k/InGaAs interfacial layer (~1nm), which can contain native oxides of InGaAs. The engineering of the high-k/InGaAs interface is therefore the key to reducing C-V hysteresis and improving device reliability. This work demonstrates the ability to reduce border trap density with forming gas annealing (5% H2 / 95% N2) in the range 3500C~4500C for Al2O3/InGaAs and HfO2/InGaAs MOS structures. Moreover, it is observed that C-V hysteresis increases with a power law dependence with the increasing stress time (in accumulation) at the initial stage of stressing and tends to reach a plateau at sufficiently long stress times due to the filling of almost all the pre-existing border traps. This therefore provides a method to estimate the total trap density under certain oxide field. Furthermore, a combined C-V and hard x-ray photoelectron spectroscopy (HAXPES) study was performed on Al2O3/InGaAs MOS structure, revealing a partially pinned Al2O3/InGaAs interface. The Fermi level position at zero gate bias was calculated using both techniques, and a reasonable agreement was achieved. This combined study thus provides more certainty on the interface state profile extractions."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["An investigation of border traps and interface states in high-k/InGaAs metal-oxide-semiconductor systems"]}]}],"canonical_facts":{"dc:contributor.advisor":["Hurley, Paul K.","Monaghan, Scott"],"dc:creator":["Lin, Jun"],"dc:date.accessioned":["2018-01-30T12:47:49Z"],"dc:date.available":["2018-01-30T12:47:49Z"],"dc:date.issued":["2017"],"dc:description.abstract":["One approach to saving energy in metal-oxide-semiconductor field effect transistors (MOSFETs) is to replace SiO2/Si structure with high dielectric constant (high-k) oxides on high mobility channel materials (e.g. InGaAs), which have the potential to achieve a comparable on current and operating frequency to silicon, but at a reduced supply voltage. In this thesis, investigation into border traps (or charge trapping) and interface states, both of which can induce device instability, in HfO2/InGaAs and Al2O3/InGaAs metal-oxidesemiconductor (MOS) structures was carried out with an emphasis on the characterization of border traps using capacitance-voltage (C-V) hysteresis measurement. The charge trapping is observed to be mainly a reversible process. The trapped charge is predominantly localized as a sheet charge near/at the high-k/InGaAs interfacial layer (~1nm), which can contain native oxides of InGaAs. The engineering of the high-k/InGaAs interface is therefore the key to reducing C-V hysteresis and improving device reliability. This work demonstrates the ability to reduce border trap density with forming gas annealing (5% H2 / 95% N2) in the range 3500C~4500C for Al2O3/InGaAs and HfO2/InGaAs MOS structures. Moreover, it is observed that C-V hysteresis increases with a power law dependence with the increasing stress time (in accumulation) at the initial stage of stressing and tends to reach a plateau at sufficiently long stress times due to the filling of almost all the pre-existing border traps. This therefore provides a method to estimate the total trap density under certain oxide field. Furthermore, a combined C-V and hard x-ray photoelectron spectroscopy (HAXPES) study was performed on Al2O3/InGaAs MOS structure, revealing a partially pinned Al2O3/InGaAs interface. The Fermi level position at zero gate bias was calculated using both techniques, and a reasonable agreement was achieved. This combined study thus provides more certainty on the interface state profile extractions."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://hdl.handle.net/10468/5349"],"dc:language.iso":["en"],"dc:publisher":["University College Cork"],"dc:rights":["© 2017, Jun Lin."],"dc:rights.uri":["http://creativecommons.org/licenses/by-nc-nd/3.0/"],"dc:subject":["InGaAs MOS","Border traps","Interface states"],"dc:title":["An investigation of border traps and interface states in high-k/InGaAs metal-oxide-semiconductor systems"],"dc:type":["Doctoral thesis"],"dc:type.qualificationlevel":["Doctoral"],"dc:type.qualificationname":["PhD (Science)"]},"updated_at":"2026-07-24T01:47:55Z"}