We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing CPU-only execution with CIM-offloaded execution. For MNIST, CIM reduces CPU instruction count by 88.6% and estimated total system dynamic energy by 84.0%. Furthermore, stress-testing with the large synthetic topology demonstrates that these efficiency gains scale considerably as the CPU encounters the memory wall. Ultimately, the co-simulation framework provides a practical, full-stack approach for studying CIM integration trade-offs in embedded ML systems and for identifying when CIM-offload becomes beneficial under realistic constraints on software and device interactions.
","abstract_html":"<p>We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing CPU-only execution with CIM-offloaded execution. For MNIST, CIM reduces CPU instruction count by 88.6% and estimated total system dynamic energy by 84.0%. Furthermore, stress-testing with the large synthetic topology demonstrates that these efficiency gains scale considerably as the CPU encounters the memory wall. Ultimately, the co-simulation framework provides a practical, full-stack approach for studying CIM integration trade-offs in embedded ML systems and for identifying when CIM-offload becomes beneficial under realistic constraints on software and device interactions.</p>","abstract_has_math":false,"creators":["Lee, Belsen"],"institution":null,"degree_name":null,"degree_level":"Thesis","degree_discipline":"Electrical Engineering and Computer Science","degree_department":null,"school":null,"contributors":["Dr. Tom Springer","Dr. Peiyi Zhao","Dr. Mark Harrison"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2026,"date_issued":"2026-05-01T07:00:00Z","date_published":"2026-05-01T07:00:00Z","updated_at":"2026-07-24T01:38:47Z","subjects":["Compute-in-Memory","Co-Simulation","QEMU","SystemC","RISC-V","Edge ML","Computer and Systems Architecture","Hardware Systems","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://digitalcommons.chapman.edu/eecs_theses/10","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Dr. Tom Springer","Dr. Peiyi Zhao","Dr. Mark Harrison"]},{"key":"dc:creator","label":"Author","values":["Lee, Belsen"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"thesis:degree_discipline","label":"Discipline","values":["Electrical Engineering and Computer Science"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Thesis"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Compute-in-Memory","Co-Simulation","QEMU","SystemC","RISC-V","Edge ML","Computer and Systems Architecture","Hardware Systems","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://digitalcommons.chapman.edu/eecs_theses/10"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing CPU-only execution with CIM-offloaded execution. For MNIST, CIM reduces CPU instruction count by 88.6% and estimated total system dynamic energy by 84.0%. Furthermore, stress-testing with the large synthetic topology demonstrates that these efficiency gains scale considerably as the CPU encounters the memory wall. Ultimately, the co-simulation framework provides a practical, full-stack approach for studying CIM integration trade-offs in embedded ML systems and for identifying when CIM-offload becomes beneficial under realistic constraints on software and device interactions.
"]},{"key":"dc:source","label":"Dc Source","values":["B. Lee, \"A full system co-simulation platform for evaluating edge machine learning inference using compute-in-memory,\" M. S. thesis, Chapman University, Orange, CA, 2026. https://doi.org/10.36837/chapman.000735"]},{"key":"dc:title","label":"Title","values":["A Full System Co-Simulation Platform for Evaluating Edge Machine Learning Inference Using Compute-in-Memory"]}]}],"canonical_facts":{"dc:contributor":["Dr. Tom Springer","Dr. Peiyi Zhao","Dr. Mark Harrison"],"dc:creator":["Lee, Belsen"],"dc:description.abstract":["We present a full-system co-simulation platform for evaluating embedded machine learning (ML) inference using compute-in-memory (CIM). CIM architectures aim to reduce data movement overhead by performing matrix operations in memory, but end-to-end benefits depend on system-level integration costs that are difficult to assess with isolated hardware models alone. To address this gap, we develop an integrated RISC-V QEMU-SystemC co-simulation environment that allows standard embedded Linux to interact with a transaction-level CIM accelerator model via memory-mapped I/O, direct memory access (DMA), and interrupts. To evaluate performance, we benchmark an MNIST image inference workload and a synthetic fully connected neural network, comparing CPU-only execution with CIM-offloaded execution. For MNIST, CIM reduces CPU instruction count by 88.6% and estimated total system dynamic energy by 84.0%. Furthermore, stress-testing with the large synthetic topology demonstrates that these efficiency gains scale considerably as the CPU encounters the memory wall. Ultimately, the co-simulation framework provides a practical, full-stack approach for studying CIM integration trade-offs in embedded ML systems and for identifying when CIM-offload becomes beneficial under realistic constraints on software and device interactions.
"],"dc:identifier":["https://digitalcommons.chapman.edu/eecs_theses/10"],"dc:source":["B. Lee, \"A full system co-simulation platform for evaluating edge machine learning inference using compute-in-memory,\" M. S. thesis, Chapman University, Orange, CA, 2026. https://doi.org/10.36837/chapman.000735"],"dc:subject":["Compute-in-Memory","Co-Simulation","QEMU","SystemC","RISC-V","Edge ML","Computer and Systems Architecture","Hardware Systems","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["A Full System Co-Simulation Platform for Evaluating Edge Machine Learning Inference Using Compute-in-Memory"],"thesis:degree_discipline":["Electrical Engineering and Computer Science"],"thesis:degree_level":["Thesis"]},"updated_at":"2026-07-24T01:38:47Z"}