Adaptive digital multiprocessor systems for image processing applications
type: CreativeWork
description: The aim of the project was to develop the digital processing capabilities of adaptive multiprocessor systems in image processing applications. Adaptive architectural configurations are the main area of investigation. Chapter 1 briefly reviews image processing and outlines various associated image processing routines. Chapter 2 describes various forms of system parallelism for image processing operations, and various interconnection networks are outlined and discussed. Chapter 3 discusses four methods of decreasing the execution time of image processing algorithms. Image partitioning and adaptivity of a proposed system is discussed. Some system architectural considerations are discussed, and a brief comparison of crossbar, multiple bus and partial bus interconnection networks is presented. The redundancy in the partial bus is discussed and a new interconnection network is proposed. Chapter 4 outlines the design, construction and testing of arbitration, processor and memory circuits for a section of the proposed multiprocessor system. Chapter 5 discusses four methods of evaluating system performance and compares the performances of the multiple bus, partial bus and modified partial bus. Conclusions for the project are given in Chapter 6 and a proposal for further work is presented.
abstract: The aim of the project was to develop the digital processing capabilities of adaptive multiprocessor systems in image processing applications. Adaptive architectural configurations are the main area of investigation. Chapter 1 briefly reviews image processing and outlines various associated image processing routines. Chapter 2 describes various forms of system parallelism for image processing operations, and various interconnection networks are outlined and discussed. Chapter 3 discusses four methods of decreasing the execution time of image processing algorithms. Image partitioning and adaptivity of a proposed system is discussed. Some system architectural considerations are discussed, and a brief comparison of crossbar, multiple bus and partial bus interconnection networks is presented. The redundancy in the partial bus is discussed and a new interconnection network is proposed. Chapter 4 outlines the design, construction and testing of arbitration, processor and memory circuits for a section of the proposed multiprocessor system. Chapter 5 discusses four methods of evaluating system performance and compares the performances of the multiple bus, partial bus and modified partial bus. Conclusions for the project are given in Chapter 6 and a proposal for further work is presented.
author: Brady, Martin
language: en
keywords: H600 - Electronic & electrical engineering
date published: 1986-10
date modified: 2026-07-24T01:36:10Z
provider: University of Central Lancashire
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: Lancashire Polytechnic