Error Floor Analysis of Quasi-Cyclic LDPC and Spatially Coupled-LDPC Codes and Construction of Codes with Low Error Floor

Forward error-correcting (FEC) codes play an important role in transmitting data with extremely high reliability through modern communication systems. In this thesis, we study the design and analysis of low-density parity-check (LDPC) codes in general and spatially coupled (SC) LDPC codes, in particular. At first, we analyze the error floor performance of finite-length protograph-based spatially coupled LDPC codes in terms of their design parameters. We conduct a comprehensive analysis to show that the parameter syndrome former memory plays the main role in the average number of cycles and trapping sets in the Tanner graph of finite-length SC-LDPC codes. This, in fact, gives an insight into the error floor performance of protograph-based SC-LDPC codes, and demonstrates the superiority of these codes in the error floor region, compared to their block code counterparts.To complement the theoretical analysis conducted in the first stage of this research, we develop corresponding design techniques to construct high-performance quasi-cyclic (QC)-LDPC and SC-LDPC codes. Our design approach is aimed at improving the performance of finite-length (SC) LDPC codes while maintaining the decoder complexity and latency small. The improvement in error floor is achieved by minimizing (elimination of) the most harmful trapping set (TS)s. We present two design approaches: 1) imposing simple conditions on the small cycles to eliminate specific classes of trapping sets, 2) developing a search-based design technique such that specific trapping sets are targeted for minimization/elimination. Our constructed QC-LDPC and time-invariant SC-LDPC codes are superior to the state-of-the-art both in terms of their error floor performance and their low decoding latency and complexity.Finally, we look into the design of finite-length time-invariant QC SC-LDPC codes with a small constraint length and a specific girth. In this respect, different scenarios for the construction process are proposed such that the final QC SC-LDPC code has a specific girth of 6 or 8 with a small constraint length. Bounds on memory and lifting degree are derived accordingly to fulfill the girth constraint associated with the specific scenario. Numerical results are provided to compare with the proposed theoretical bounds.

Name thesis:degree_name

Doctor of Philosophy (Ph.D.)

Level thesis:degree_level

Doctoral

Discipline thesis:degree_discipline

Engineering, Electrical and Computer

Grantor dc:publisher

Carleton University

Year dc:date.issued

2021

Author dc:creator

• Naseri, Sima

Statement dc:rights

• Copyright © 2021 the author(s). Theses may be used for non-commercial research, educational, or related academic purposes only. Such uses include personal study, research, scholarship, and teaching. Theses may only be shared by linking to Carleton University Institutional Repository and no part may be used without proper attribution to the author. No part may be used for commercial purposes directly or indirectly via a for-profit platform; no adaptation or derivative works are permitted without consent from the copyright owner.

Language dc:language.iso

en

DOI

10.22215/etd/2021-14438

OAI identifier oai:identifier

oai:carleton.scholaris.ca:20.500.14718/42255