Python based FPGA design-flow

This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures.

Grantor dc:publisher.institution

Department of Electrical Engineering

Year dc:date.issued

2016

Author dc:creator

• New, Wesley

Advisors dc:contributor.advisor

• Inggs, Michael
• Winberg, Simon

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/11427/20339

OAI identifier oai:identifier

oai:open.uct.ac.za:11427/20339