Study of the TR Synchronization and Video Conversion Unit

This dissertation describes the design and testing of a model of the Synchronization and Video Conversion Unit (SVCU), a subsystem of the tracking radar (TR) at Denel Overberg Test Range (OTR). The SVCU synchronizes all the radar sub-systems and also converts the returned RF target signals to digital numbers. The technology within the SVCU is outdated and spares are scarce if not unattainable. This study forms the first phase of the development of a new SVCU and will determine the specifications of the hardware needed to build the replacement. Models of the transmit and receive chain of the radar were first developed in SystemVueTM. A comprehensive literature review was then done, yielding an accurate model of the current SVCU. The radar model was run, with simulated target and scene parameters, and its output fed into the SVCU model. The output of the SVCU was then processed by a CFAR detector and gated tracking algorithms implemented in MathLang and Python. The simulated target was correctly identified in the range-Doppler plane. The tracking gates (used to measure range and Doppler) were then corrupted with jitter, rise- time and offsets. A statistical analysis was done on the effect of these impurities on the radar measurements. A new SVCU architecture, utilizing high speed ADCs and digital integrators, was then tested. The effects of non-linearities (DNL and INL) in the ADC and phase noise on the ADC sample clock on the radar measurements were analysed. The jitter on the transmit sync (TX), the ADC sample clock and tracking gates were found to be the most critical aspects of the SVCU. To meet the specified measurement accuracy of the radar, the root-sum-square of the jitter on these syncs (jitter budget) must not exceed 30 nanoseconds. A case study was then done to determine the jitter budget achievable in an FPGA-centric SVCU design. The study concluded that a jitter budget of 30 ns is achievable. Moreover, in an FPGA based design the jitter introduced by the interface sending the TX sync from the FPGA (SVCU) to the transmitter assembly will, almost entirely, determine the range accuracy of the TR. From these findings, a new SVCU, based on the RHINO board from the UCT RRSG, was recommended and the future work outlined.

Grantor dc:publisher.institution

Department of Electrical Engineering

Year dc:date.issued

2012

Author dc:creator

• Abraham, Justin Kuruvilla

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/11427/14137

OAI identifier oai:identifier

oai:open.uct.ac.za:11427/14137