Firmware and gateway for the ACE1 reconfigurable accelerator card

This thesis describes the continued work on the in-house designed FPGA based co-processor daughtercard referred to as ACE1. The aim: to create an ecosystem incorporating firmware, bootstrapping code, drivers and a development environment to create a seamless environment. Challenges in setting up and debugging the interface that connects the coprocessor daughtercard to the host server include: problems with the power network, the edge connectors and timing problems with the primary protocol which prevented host-based communications. The options include allowing the daughtercard to function in a stand-alone fashion and we present a gateware solution that allows users to select from a number of alternatives for each of the layers in the Open Systems Interconnect networking model.

Grantor dc:publisher.institution

Department of Electrical Engineering

Year dc:date.issued

2011

Author dc:creator

• Thorne, Nicholas James

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/11427/10926

OAI identifier oai:identifier

oai:open.uct.ac.za:11427/10926