Carrier mobility of downscaled amorphous semiconductors exemplified by hydrogenated amorphous silicon

Initially rooted in visual displays, thin film transistors (TFTs) have over the decades extensively expanded their applications into sensors and flexible electronics that collaboratively build many of today’s and the next-generation’s Internet of Things (IoT) facilities. Amorphous semiconductors are among the most favoured channel semiconductors in TFTs because of their irreplaceable merits such as large-area uniformity, low cost and low thermal budget which are essential to the above use cases. Nevertheless, the utilisation of amorphous semiconductors seems to inevitably bring about degraded electrical performance compared with the cases where their monocrystalline counterparts are used. The issue of low carrier mobility is one example, which needs to be solved in light of the increasing demands on the speed of IoT hardware. For a long time, endeavours on improving the carrier mobility of amorphous semiconductors have only targeted material- and device-level optimisations which often show low efficacy, low reproducibility, and/or lead to compromises in other metrics. In this thesis, considering the presence of short- and medium-range order in amorphous semiconductors which is anticipated to play a greater role at shorter length scales, a novel strategy is proposed which utilises the general trend in the semiconductor industry, i.e., downscaling, to fundamentally improve the carrier mobility of amorphous semiconductors. To validate this hypothesis, a holistic theoretical framework is established. The theory focusses on the universal band tails found in the density of states (DOS) of amorphous semiconductors, which affects charge transport. Using hydrogenated amorphous silicon (a-Si:H) as an example, excess valence band and conduction band electrons stemming from the distortion of bonds are modelled according to a Gaussian probability distribution with spatial correlations associated with the short- and medium-range order. The model reproduces the DOS distribution of a-Si:H with two fitting parameters, reveals the attributes of localised band tail states, and yields modifications to the multiple trapping and release (MTR) transport theory which dominates room-temperature conduction of a-Si:H and many other amorphous semiconductors. This scalable model is then applied to the nanoscale, and estimates that the intrinsic DC mobility of a-Si:H can increase from ~ 1 cm2/(V s) to ~ 12 cm2/(V s) after the material is downscaled to a 10-nm gap. The outcomes of the theoretical work in this thesis offer guidance on follow-on experiments, the preliminary phase of which has been attempted. With future device-level optimisations, the strategy proposed in this thesis would enable a great leap of IoT hardware; examples include the realisation of high-speed flexible microprocessors for edge computing.

Name dc:type.qualificationname

Doctor of Philosophy (PhD)

Level dc:type.qualificationlevel

Doctoral

Grantor dc:publisher.institution

University of Cambridge

Year dc:date.issued

2025

Author dc:creator

• Luo, Yuezhou

Advisor dc:contributor.advisor

• Flewitt, Andrew

• amorphous semiconductor
• downscaling
• carrier mobility
• material modelling
• electronic structure
• charge transport
• lithography
• flexible electronics
• thin film transistor
• amorphous silicon

Licence

• https://www.repository.cam.ac.uk/bitstreams/98d23903-8d40-438b-af07-55603d1f3f31/download
• https://creativecommons.org/licenses/by/4.0/

Language dc:language

eng

Author Identifier

0009-0008-7878-717X

OAI identifier oai:identifier

oai:www.repository.cam.ac.uk:1810/390576