Novel Thin Film Nanogap Device Fabrication And 3D Integration Enabled By Adhesion Lithography

There has been an increasing demand for transparent and flexible electronics/large-area electronics (LAE) due to the rapid growth of the Internet of Things (IoT) in recent decades. New materials, such as organic semiconductors, amorphous/nanocrystalline materials, metal oxides, and 2-dimensional/3-dimensional (2D/3D) nano/micro-structure materials play an important role in LAE. Due to the nature of these materials, conventional fabrication processes for Si and its oxides, as well as III-V materials, are not compatible anymore. Many new deposition methods, such as ink jet printing, gravure, and roll-to-roll coating have already been finely developed and used to deposit and pattern these new materials over a large area at low temperatures without costing too much in the past 20 years. Alongside the development of deposition of these new materials, the feature size of the devices used in LAE becomes smaller which is parallel to the downscaling of the devices in the integrated circuits (IC) industry. According to Moore’s law, the feature size of devices in the electronics industry has already entered the nanoscale era. Therefore, the combination of nanoscale device feature size and low-temperature and low-cost fabrication processes for LAE is now drawing great attention in many ways. Hence, there is a requirement to seek proper nanoscale patterning methods for LAE which combine large-volume fabrication and high resolution simultaneously. The advent of Adhesion Lithography (A-Lith) by Beesley et al. in 2014 provides a new way of nanoscale patterning for LAE processes. It is a self-alignment process that makes use of the characteristics of the self-assembled monolayer (SAM) on specific materials to alter their surface energy, which then allows the direct removal/peeling of other materials overlapped with the SAM-treated materials. This technique is currently used in creating metal electrodes separated by sub-10 nm length and then using these planar nanogap electrodes to fabricate novel planar devices. Importantly, it is an inexpensive, scalable, high-resolution, and high-throughput technique that has the potential to be scaled up for manufacturing in the industry. Referring to this progress in adhesion lithography; this thesis explores more possibilities in the fabrication and applications of adhesion lithography. The works presented in this thesis are in three aspects: basic nanogap electrode fabrication, new device fabrication, and then system-level fabrication. Firstly, at the basic nanogap fabrication level, a total of ten new combinations (two symmetric and eight asymmetric) of nanogap electrodes were fabricated and characterized. Four nanogap electrode combinations: Al/Au, Al/Al, Al/Ti, and Ti/Al among the ten used in this work showed good quality with a gap length achieved sub-10 nm and high yield rates of up to 90%. Next, in device-level fabrication, this thesis shows the development of three-terminal devices which combine conventional photolithography and adhesion lithography to satisfy large-area fabrication and high resolution simultaneously. Both symmetric and asymmetric nanogap electrodes have been created and optimized to fabricate three-terminal nanogap devices. Device characterization and a physics-based model demonstrate that asymmetric three-terminal nanogap devices appear to behave like depletion-mode gated Schottky diodes and symmetric three-terminal nanogap devices behave like depletion-mode metal-insulator tunneling transistors (MITT). Also, both devices are air-stable and have very small gate leakage currents. Finally, in system-level fabrication, this thesis introduces a simple way of fabricating scalable multiple-layer nanogap device arrays on the same substrate area. Such a 3D integration method of nanogap devices increases device density and permits greater system complexity without increasing substrate area. It opens the possibility of combining current Si Integrated Circuits (IC) with novel scalable nanogap devices fabricated as a back-end process allowing tailored functionality. The double-layer a-IGZO nanogap Schottky diode arrays were fabricated with a good yield of up to 90%. DC characterization revealed rectification ratios for both layers of diodes up to 104, and both lateral and vertical current paths inside the system. The stacked nanogap device structure shows good stability, repeatability, and reliability.

Name dc:type.qualificationname

Doctor of Philosophy (PhD)

Level dc:type.qualificationlevel

Doctoral

Grantor dc:publisher.institution

University of Cambridge

Year dc:date.issued

2022

Author dc:creator

• Zeng, Yuqi

Advisor dc:contributor.advisor

• Flewitt, Andrew

• Large Area Electronics
• Nanoscale fabrication
• Nanogap devices
• Sub-10 nm gap

Licence

• https://www.rioxx.net/licenses/all-rights-reserved/

Language dc:language

eng

DOI dc:identifier.doi

https://doi.org/10.17863/CAM.91197

OAI identifier oai:identifier

oai:www.repository.cam.ac.uk:1810/343775