Cmos Design of an 8-Bit 1MS/S Successive Approximation Register ADC

<p>Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.</p> <p>This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm</p>

Name thesis:degree_name

MS in Electrical Engineering

Discipline thesis:degree_discipline

Electrical Engineering

Year dc:date.available

2019

Author dc:creator

• Ganguli, Ameya Vivekanand

Contributors dc:contributor

• Tina Smilkstein

• SAR
• analog-to-digital converter
• charge re-distribution
• asynchronous
• dynamic comparator
• monotonic switching
• Electrical and Computer Engineering
• Electrical and Electronics
• VLSI and Circuits, Embedded and Hardware Systems

Identifier

10.15368/theses.2019.55

OAI identifier oai:identifier

oai:digitalcommons.calpoly.edu:theses-3463