Asynchronous MIPS Processors: Educational Simulations

The system clock has been omnipresent in most mainstream chip designs. While simplifying many design problems the clock has caused the problems of clock skew, high power consumption, electromagnetic interference, and worst-case performance. In recent years, as the timing constraints of synchronous designs have been squeezed ever tighter, the efficiencies of asynchronous designs have become more attractive. By removing the clock, these issues can be mitigated. How- ever, asynchronous designs are generally more complex and difficult to debug. In this paper I discuss the advantages of asynchronous processors and the specifics of some asynchronous designs, outline the roadblocks to asynchronous processor design, and propose a series of asynchronous designs to be used by students in tandem with traditional synchronous designs when taking an undergraduate computer architecture course.

Name thesis:degree_name

MS in Computer Science

Discipline thesis:degree_discipline

Computer Science

Year dc:date.available

2010

Author dc:creator

• Webb, Robert L

Contributors dc:contributor

• Chris Lupo

• Asynchronous
• architecture
• logic
• Computer and Systems Architecture
• Computer Engineering
• Computer Sciences
• Digital Circuits
• Electrical and Electronics
• Power and Energy
• VLSI and Circuits, Embedded and Hardware Systems

Identifier

10.15368/theses.2010.144

OAI identifier oai:identifier

oai:digitalcommons.calpoly.edu:theses-1399