{"id":{"repo_id":"calgary","oai_identifier":"oai:ucalgary.scholaris.ca:1880/110709"},"canonical_url":"https://search.dev.ndltd.org/etd/calgary/oai:ucalgary.scholaris.ca:1880/110709","repository":{"repo_id":"calgary","name":"University of Calgary","base_url":"https://ucalgary.scholaris.ca/server/oai/request"},"display":{"title":"Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing","abstract":"Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%.","abstract_html":"Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%.","abstract_has_math":false,"creators":["Farshidi, Ali"],"institution":"Schulich School of Engineering","degree_name":"Master of Science (MSc)","degree_level":null,"degree_discipline":"Engineering – Electrical & Computer","degree_department":null,"school":null,"contributors":[],"advisors":["Behjat, Laleh","Rakai, Logan M."],"committee_chairs":[],"committee_members":["Dimitrov, Vassil","Yanushkevich, Svetlana N."],"year":2019,"date_issued":"2019-08-09","date_published":"2019-08-09","updated_at":"2026-07-24T01:30:36Z","subjects":["Very Large Scale Integration","Clock Network Buffer Sizing","VLSI","Delay Modeling","Geometric Programming"],"languages":["eng"],"rights":["University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. 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In this thesis, a new delay model is proposed for clock networks that is capable of estimating clock signal delay with significantly improved accuracy in a relatively low runtime. This model is developed using Least square fitting by employing data oriented training. The developed model is formulated in the form of posynomials which makes it a suitable option for application in geometric programming gate and clock network sizing optimization frameworks. The experimental results demonstrate the effectiveness of the proposed delay model in predicting the delay at the timing critical clock sinks in the clock network, i.e. sinks with minimum and maximum delays, and the estimated values are, on average, 20 ps closer than the Elmore values to the reference circuit simulator tool, ngspice. This is while the runtime of the proposed delay model is negligible compared to the ngspice simulations. This helps designers obtain accurate delay estimations in low runtime for quick optimization iterations. In addition, a clock network buffer sizing approach is developed which includes an objective function with geometric programming format considering two competing objectives, power consumption and clock skew. The clock slew and technology constraints are also integrated into this optimization problem. The clock network buffer sizing experiments show significant improvements compared to the initial clock networks in terms of clock skew, up to 183 ps, while the power consumption improves for all test cases, on average by 54%."]},{"key":"dc:title","label":"Title","values":["Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing"]}]}],"canonical_facts":{"dc:contributor.advisor":["Behjat, Laleh","Rakai, Logan M."],"dc:contributor.committeemember":["Dimitrov, Vassil","Yanushkevich, Svetlana N."],"dc:creator":["Farshidi, Ali"],"dc:date":["2019-11"],"dc:date.accessioned":["2019-08-12T17:05:09Z"],"dc:date.available":["2019-08-12T17:05:09Z"],"dc:date.issued":["2019-08-09"],"dc:description.abstract":["Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. 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You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission."],"dc:subject":["Very Large Scale Integration","Clock Network Buffer Sizing","VLSI","Delay Modeling","Geometric Programming"],"dc:title":["Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing"],"dc:type":["master thesis"],"thesis:degree_discipline":["Engineering – Electrical & Computer"],"thesis:degree_name":["Master of Science (MSc)"],"thesis:institution_name":["University of Calgary"]},"updated_at":"2026-07-24T01:30:36Z"}