Modern VLSI Placement Observing Technology Constraints

The placement process is a key step in physical design as it directly impacts circuit performance, area, power consumption, reliability, and the quality of other steps, such as routing, in the physical design flow. The placement problem has become ever more complex and challenging due to a wide variety of intricate constraints and design rules imposed by modern technology processes on the Very Large Scale Integration (VLSI) design process. Any constraint not only makes the placement problem challenging; but also can degrade the quality of the objectives optimized during the placement process or other steps in the physical design flow. In addition, with increases in complicated constraints and in the number of circuit components, the runtime and scalability of algorithms used in the placement process has become critical. In this thesis, a high-performance modern technology-driven placer called Eh?Placer is presented to address the challenges rising in modern technology processes. Eh?Placer is a comprehensive placement framework that provides solutions while observing modern technology constraints and routability, and optimizing wire length. Addressing the sheer number of circuit components using parallel computing methods makes Eh?Placer one of the fastest placement tools. In addition to Eh?Placer, a robust and fast legalization framework developed for standard-cell placement is presented. The proposed framework effectively legalizes input placements while minimizing the maximum and average cell movements using a novel global network-flow based approach. In addition, the developed legalizer is the only network flow based approach to observe modern technology constraints. In contrast to the traditional network flow based legalizers, areas with high cell utilization are legalized by finding several candidate paths where there is no need for the post-process step. The proposed legalizer is scalable and robust with respect to the floorplan complexity.

Name thesis:degree_name

Doctor of Philosophy (PhD)

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor dc:publisher.institution

Graduate Studies

Year dc:date.issued

2017

Author dc:creator

• Karimpour Darav, Nima

Advisors dc:contributor.advisor

• Behjat, Laleh
• Westwick, David T

Committee members dc:contributor.committeemember

• Madden, Patrick H
• Kennings, Andrew Albert
• Rakai, Logan Marshall
• Yanushkevich, Svetlana
• Dimitrov, Vassil Simeonov

• Computer Science
• Engineering--Electronics and Electrical

Statement dc:rights

• University of Calgary graduate students retain copyright ownership and moral rights for their thesis. You may use this material in any way that is permitted by the Copyright Act or through licensing that has been assigned to the document. For uses that are not allowable under copyright legislation or licensing, you are required to seek permission.

Language dc:language.iso

eng

DOI

http://dx.doi.org/10.11575/PRISM/26969

OAI identifier oai:identifier

oai:ucalgary.scholaris.ca:11023/3858