Dataflow based design suite for the development and management of multi-functional reconfigurable systems

Embedded systems development constitutes an extremely challenging scenario for the designers since several constraints have to be meet at the same time. Flexibil- ity, performance and power efficiency are typically colliding requirements that are hardly addressed together. Reconfigurable systems provide a valuable alternative to common architectures to challenge contemporarily all those issues. Such a kind of systems, and in particular the coarse grained ones, exhibit a certain level of flexi- bility while guaranteeing strong performance. However they suffer of an increased design and management complexity. In this thesis it is discussed a fully automated methodology for the development of coarse grained reconfigurable platforms, by exploiting dataflow models for the de- scription of the desired functionalities. The thesis describes, actually, a whole design suite that offers, besides the reconfigurable substrate composition, also structural optimisation, dynamic power management and co-processing support. All the pro- vided features have been validated on different signal, image and video processing scenarios, targeting either FPGA and ASIC.

Grantor dc:publisher

Università degli Studi di Cagliari

Year dc:date

2016

Author dc:creator

• SAU, CARLO

• accelleratori hardware
• coarse grained reconfigurability
• controllo del consumo di potenza
• dataflow model of computation
• hardware accelerators
• modello di computazione dataflow
• paradigma riconfigurabile
• power management
• reconfigurable computing
• riconfigurabilità a grana grossa
• Settore ING-INF/01 - Elettronica

Statement dc:rights

• info:eu-repo/semantics/openAccess
• license:Non specificato

Language dc:language

eng

Handle dc:identifier

http://hdl.handle.net/11584/266751

OAI identifier oai:identifier

oai:iris.unica.it:11584/266751