Studio e implementazione di strumenti per lo sviluppo software nei sistemi basati su FPGA.
type: CreativeWork
description: Computer market becomes every day more performance-hungry. Nowadays microprocessor based systems are not able to relevant good performances in various application domains. The classic Von Neumann load/store architetture is suitable for some tasks, but seems to have serious scalability issues. To tackle these issues one of the current trend in the quest for additional execution speed, provides additional processing corees in the central processing unit and to parallelize the execution of as much of the software as possible. This paradigm has potential, but its effectiveness has been limited by the difficulties involved in parallelizing software that was written for sequential execution, resulting in cumbersome dependencies. These dependencies require extensive changes in the software design paradigms if this approach means to reach its full potential. On the other hand, reconfigurable devices have proven to be very scalable for a large class of applications and they offer potential application performance improvements beyond those predicted by Moore's Law. Among the different templates proposed in literature in the field or reconfigurable computing, Configurable System-on-a-Chip (CSoC) are emerging as a convincing trade-off between efficiency and flexibility. This kind of systems are often composed by one or more CPUs coupled with a Field Programmable Gate Array (FPGA), and it can be demonstrated that they can run applications two orders of magnitude faster than traditional on CPUs. This performance speedup with respect to microprocessors relies basically in the opportunity of using dedicated reconfigurable hardware to exploit the inherent parallelism of an algorithm. One of the key issues in using such systems is related to the software development activity. A programmer typically uses a high level language to implement its algorithms but, to exploit the full potential of a reconfigurable system, a deeper knowledge of the target architetture and of digital design te…
abstract: Computer market becomes every day more performance-hungry. Nowadays microprocessor based systems are not able to relevant good performances in various application domains. The classic Von Neumann load/store architetture is suitable for some tasks, but seems to have serious scalability issues. To tackle these issues one of the current trend in the quest for additional execution speed, provides additional processing corees in the central processing unit and to parallelize the execution of as much of the software as possible. This paradigm has potential, but its effectiveness has been limited by the difficulties involved in parallelizing software that was written for sequential execution, resulting in cumbersome dependencies. These dependencies require extensive changes in the software design paradigms if this approach means to reach its full potential. On the other hand, reconfigurable devices have proven to be very scalable for a large class of applications and they offer potential application performance improvements beyond those predicted by Moore's Law. Among the different templates proposed in literature in the field or reconfigurable computing, Configurable System-on-a-Chip (CSoC) are emerging as a convincing trade-off between efficiency and flexibility. This kind of systems are often composed by one or more CPUs coupled with a Field Programmable Gate Array (FPGA), and it can be demonstrated that they can run applications two orders of magnitude faster than traditional on CPUs. This performance speedup with respect to microprocessors relies basically in the opportunity of using dedicated reconfigurable hardware to exploit the inherent parallelism of an algorithm. One of the key issues in using such systems is related to the software development activity. A programmer typically uses a high level language to implement its algorithms but, to exploit the full potential of a reconfigurable system, a deeper knowledge of the target architetture and of digital design te…
author: BUSONERA, GIOVANNI
language: ita
keywords: Debugging, FPGA, Partizionamento, Riconfigurabile, Settore ING-INF/01 - Elettronica
date published: 2008-03-28
date modified: 2026-07-24T01:29:59Z
provider: Università di Cagliari
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: Università degli Studi di Cagliari

PropertyValue
property ID: Handle
value: http://hdl.handle.net/11584/265951