{"id":{"repo_id":"byu","oai_identifier":"oai:scholarsarchive.byu.edu:etd-1808"},"canonical_url":"https://search.dev.ndltd.org/etd/byu/oai:scholarsarchive.byu.edu:etd-1808","repository":{"repo_id":"byu","name":"Brigham Young University","base_url":"https://scholarsarchive.byu.edu/do/oai/"},"display":{"title":"High Voltage Analog Design in a Standard Digital CMOS Process","abstract":"This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface.","abstract_html":"This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface.","abstract_has_math":false,"creators":["Beck, Riley D."],"institution":"Brigham Young University - Provo","degree_name":"MS","degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":[],"advisors":[],"committee_chairs":[],"committee_members":[],"year":null,"date_issued":"","date_published":null,"updated_at":"2026-07-24T01:28:20Z","subjects":["high voltage","analog design","bulk-driven","reverse battery","Hall-effect sensor","Electrical and Computer Engineering"],"languages":["English"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarsarchive.byu.edu/etd/809","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:creator","label":"Author","values":["Beck, Riley D."]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2005-11-17T08:00:00Z"]},{"key":"dc:publisher","label":"Institution","values":["Brigham Young University - Provo"]},{"key":"dc:type","label":"Dc Type","values":["Thesis"]},{"key":"thesis:degree_name","label":"Degree Name","values":["MS"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["high voltage","analog design","bulk-driven","reverse battery","Hall-effect sensor","Electrical and Computer Engineering"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["English"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarsarchive.byu.edu/etd/809","https://scholarsarchive.byu.edu/context/etd/article/1808/viewcontent/ETD_CISOPTR_829.pdf"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering"]},{"key":"dc:description.abstract","label":"Abstract","values":["This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface."]},{"key":"dc:format","label":"Dc Format","values":["application:pdf"]},{"key":"dc:source","label":"Dc Source","values":["Brigham Young University - Provo"]},{"key":"dc:title","label":"Title","values":["High Voltage Analog Design in a Standard Digital CMOS Process"]}]}],"canonical_facts":{"dc:creator":["Beck, Riley D."],"dc:date":["2005-11-17T08:00:00Z"],"dc:description":["Ira A. Fulton College of Engineering and Technology; Electrical and Computer Engineering"],"dc:description.abstract":["This thesis introduces high-voltage approaches that are implemented in an analog Hall-effect sensor interface. This interface has been realized in a modified 5V 0.6um CMOS process using 40V high-voltage MOS transistors that do not affect low-voltage device functionality. These circuits include a high-voltage, low-offset current sense amplifier, which achieves a common-mode input range that is within a Vtp of Vdd using a bulk-driven differential input stage. The amplifier also uses high voltage cascode devices to protect low-voltage devices that have been placed in critical matching areas to achieve a low input offset voltage of 500uV without the use of trim. A short to battery architecture is also discussed which uses a bulk-driven comparator and a PMOS blocking technique and allows for a reliable short to battery breakdown voltage without using a series blocking diode. Integration of these blocks into a standard CMOS process leads to cost savings as additional devices such as data converters and microprocessors are combined with the Hall-effect sensor interface."],"dc:format":["application:pdf"],"dc:identifier":["https://scholarsarchive.byu.edu/etd/809","https://scholarsarchive.byu.edu/context/etd/article/1808/viewcontent/ETD_CISOPTR_829.pdf"],"dc:language":["English"],"dc:publisher":["Brigham Young University - Provo"],"dc:source":["Brigham Young University - Provo"],"dc:subject":["high voltage","analog design","bulk-driven","reverse battery","Hall-effect sensor","Electrical and Computer Engineering"],"dc:title":["High Voltage Analog Design in a Standard Digital CMOS Process"],"dc:type":["Thesis"],"thesis:degree_name":["MS"]},"updated_at":"2026-07-24T01:28:20Z"}