Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion

This thesis presents four-quadrant CMOS current-mode multiplier architectures based on the bipolar Gilbert cell multiplier architecture. Multipliers are designed using the CMOS subthreshold region to take advantage of the subthreshold exponential I-V relationship that closely matches bipolar modeling. It is discovered that biasing to remove drift current components and to address higher order effects such as ideality factor mismatch, threshold mismatch, body effect, and short channel effects, is important to provide a linear multiplier. It is also shown that distortion caused by device size mismatch and offset input currents can be used to cancel the distortion introduced by drift currents when designing in weak and moderate inversion. This concept allows for linear multiplier designs with larger input currents which results in dramatic improvements in bandwidth over traditional weak inversion circuits. Three multiplier circuits are simulated and fabricated in an AMIS 0.35-um process. Circuits with less than 1 % nonlinear error and distortion (THD) across 100 % dynamic input range and with bandwidths greater than 100 MHz can be built. Also, low power multiplier solutions are presented that consume less than 40 nW of dynamic power.

Name thesis:degree_name

MS

Grantor dc:publisher

Brigham Young University - Provo

Author dc:creator

• Remund, Craig Timothy

• CMOS
• multiplier
• Gilbert cell
• subthreshold
• weak inversion
• moderate inversion
• low power
• nonlinear error
• ideality factor
• current-mode
• distortion
• linear
• AMIS
• Electrical and Computer Engineering

Language dc:language

English

Repository record dc:identifier

https://scholarsarchive.byu.edu/etd/208

OAI identifier oai:identifier

oai:scholarsarchive.byu.edu:etd-1207