{"id":{"repo_id":"buffalo","oai_identifier":"oai:ubir.buffalo.edu:10477/78138"},"canonical_url":"https://search.dev.ndltd.org/etd/buffalo/oai:ubir.buffalo.edu:10477/78138","repository":{"repo_id":"buffalo","name":"Buffalo","base_url":"https://ubir.buffalo.edu/oai/request"},"display":{"title":"High Performance and Energy Efficiency in Network on Chip (NoC) Design","abstract":"Ph.D.","abstract_html":"Ph.D.","abstract_has_math":false,"creators":["Yan, Pengzhan"],"institution":"State University of New York at Buffalo","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["Sridhar, Ramalingam","Computer Science and Engineering"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2018,"date_issued":"2018-06-28T20:34:47Z","date_published":"2018-06-28T20:34:47Z","updated_at":"2026-07-27T19:05:09Z","subjects":["computer science"],"languages":["eng"],"rights":["Users of works found in University at Buffalo Institutional Repository (UBIR) are responsible for identifying and contacting the copyright owner for permission to reuse. University at Buffalo Libraries do not manage rights for copyright-protected works and cannot assist with permissions.","Copyright retained by author."],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"http://hdl.handle.net/10477/78138","outbound_label":"Handle","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Sridhar, Ramalingam","Computer Science and Engineering"]},{"key":"dc:creator","label":"Author","values":["Yan, Pengzhan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2018-06-28T20:34:47Z","2018","2018-05-28 20:46:32"]},{"key":"dc:publisher","label":"Institution","values":["State University of New York at Buffalo"]},{"key":"dc:type","label":"Dc Type","values":["Text","Dissertation"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["computer science"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["Users of works found in University at Buffalo Institutional Repository (UBIR) are responsible for identifying and contacting the copyright owner for permission to reuse. University at Buffalo Libraries do not manage rights for copyright-protected works and cannot assist with permissions.","Copyright retained by author."]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["http://hdl.handle.net/10477/78138"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Ph.D.","With Moore‘s law fading, presence of billions of transistors on a single chip, and diminishing performance from uniprocessor architectures, multicore chips are emerging as the prevailing architecture in both application-specific and general- purpose markets. As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth continues to gain im-portance, leading recently to multicore chips interconnected with on-chip net-works. Networks-on-Chip (NoC) is widely regarded as a promising approach for addressing communication challenges affiliated with Chip Multi-Processors (CMPs) in the face of further increases in integration density. However, through-put, energy efficiency and routing algorithms become more challenging in NoC design. To address throughput and energy efficiency, we evaluate Virtual-channel Allocation (VA), Switch Allocation (SA) in terms of matching quality, delay, area and power using RTL implementation. Based on the results of this study, we propose centralized priority management allocation (CPMA) router archi-tecture to improve matching quality, delay, area, and energy efficiency. By co-ordinating arbiters’ priority in the first allocation stage, CPMA increases the matching quality. The centralized priority unit can also reduce each arbiters de-sign complexity. The improvement of matching quality and reduction of design complexity make the router more energy efficient with less area consumption. The dissertation next focuses on NoC routing algorithms. A parameter that can indicate the traffic congestion is needed for the routing algorithm to select the best path. In this dissertation, we propose predictive passing time as a pa-rameter for the routing algorithm. Instead of indicating the traffic congestion, predictive passing time reflects the time it will take the message to go through the path. This parameter makes the routing algorithm more accurate in choos-ing among different paths. In NoC, a broken router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. To solve this issue, we present a new routing algorithm that can transmit the message to the isolated PE even when the router is broken. The approaches used here in Network on Chips can be adapted to Chip Mul-tiprocessor and multicore systems."]},{"key":"dc:format","label":"Dc Format","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["High Performance and Energy Efficiency in Network on Chip (NoC) Design"]}]}],"canonical_facts":{"dc:contributor":["Sridhar, Ramalingam","Computer Science and Engineering"],"dc:creator":["Yan, Pengzhan"],"dc:date":["2018-06-28T20:34:47Z","2018","2018-05-28 20:46:32"],"dc:description":["Ph.D.","With Moore‘s law fading, presence of billions of transistors on a single chip, and diminishing performance from uniprocessor architectures, multicore chips are emerging as the prevailing architecture in both application-specific and general- purpose markets. As the core count increases, the need for a scalable on-chip communication fabric that can deliver high bandwidth continues to gain im-portance, leading recently to multicore chips interconnected with on-chip net-works. Networks-on-Chip (NoC) is widely regarded as a promising approach for addressing communication challenges affiliated with Chip Multi-Processors (CMPs) in the face of further increases in integration density. However, through-put, energy efficiency and routing algorithms become more challenging in NoC design. To address throughput and energy efficiency, we evaluate Virtual-channel Allocation (VA), Switch Allocation (SA) in terms of matching quality, delay, area and power using RTL implementation. Based on the results of this study, we propose centralized priority management allocation (CPMA) router archi-tecture to improve matching quality, delay, area, and energy efficiency. By co-ordinating arbiters’ priority in the first allocation stage, CPMA increases the matching quality. The centralized priority unit can also reduce each arbiters de-sign complexity. The improvement of matching quality and reduction of design complexity make the router more energy efficient with less area consumption. The dissertation next focuses on NoC routing algorithms. A parameter that can indicate the traffic congestion is needed for the routing algorithm to select the best path. In this dissertation, we propose predictive passing time as a pa-rameter for the routing algorithm. Instead of indicating the traffic congestion, predictive passing time reflects the time it will take the message to go through the path. This parameter makes the routing algorithm more accurate in choos-ing among different paths. In NoC, a broken router can isolate a functional processing element (PE) from other nodes, severely restricting the performance of the system. To solve this issue, we present a new routing algorithm that can transmit the message to the isolated PE even when the router is broken. The approaches used here in Network on Chips can be adapted to Chip Mul-tiprocessor and multicore systems."],"dc:format":["application/pdf"],"dc:identifier":["http://hdl.handle.net/10477/78138"],"dc:language":["eng"],"dc:publisher":["State University of New York at Buffalo"],"dc:rights":["Users of works found in University at Buffalo Institutional Repository (UBIR) are responsible for identifying and contacting the copyright owner for permission to reuse. University at Buffalo Libraries do not manage rights for copyright-protected works and cannot assist with permissions.","Copyright retained by author."],"dc:subject":["computer science"],"dc:title":["High Performance and Energy Efficiency in Network on Chip (NoC) Design"],"dc:type":["Text","Dissertation"]},"updated_at":"2026-07-27T19:05:09Z"}