Análise e construção de aceleradores em hardware para o cálculo do menor caminho em planejamento de rotas de robôs
This work proposes an analisys and optimization for the calculation of the shortest path in route planning for mobile robots. The suggested solution aims to present a high-performance alternative that can meet the time constraints necessary for robots processing . To do so, we propose an architecture focused on parallelism to be embedded in dedicated hardware. Through the exploitation of parallelism, the solution aims to present, in addition to a performance improvement, a dynamic adaptation to changes in the graph of possible movements to be analyzed, since edges could be inserted or deleted in a temporally random manner as the environment changes. This work demonstrates the architecture developed together with its results. This application graph updating process efficiently updates obstacle matrices, resulting in a remarkable 120-fold improvement for 1024-node graphs. When utilizing a cost-effective device like the Cyclone IV E, it achieves approximately 20 times the performance of an equivalent software applications.
Dijkstra, Robôtica, Robôs móveis, Estudo de rotas, Simulação (Computadores), Circuitos integrados, Integrated circuits
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