A Power Constrained 433-MHz Low Noise Amplifier

<p>Within wireless communication systems, low noise amplifiers are critical for the performance of receivers. They are primarily responsible for providing enough gain while adding little noise to overcome the noise of the subsequent stages. The LNA presented here is part of a battery-powered transceiver meant to measure crop nutrient data and relay the information. Therefore, power consumption and area become import considerations. To design for a specific power level, a power-constrained noise optimization method is used. The method sizes the amplifying transistor for a fixed source impedance, power dissipation, technology, and operating frequency. The chosen topology is the cascode stage with inductive source degeneration. This allows for an input impedance match without much added thermal noise. For area considerations, all inductors were made internal. The LNA was fabricated in a 130 nm SiGe BiCMOS8HP technology from GLOBALFOUNDRIES. Designing the amplifier for operation at 433 MHz produced a 12 dB gain, 4.9 dB noise figure, 6.3 mW power consumption, -5 dBm input referred 1 dB compression point, and unconditional stability.</p>

Name thesis:degree_name

Master of Science in Electrical Engineering (MSEE)

Level thesis:degree_level

Thesis

Year dc:date.available

2020

Author dc:creator

• Alvarez Arellano, Pablo

Advisor dc:contributor.advisor

• Mantooth, H. Alan

Contributors dc:contributor

• Dix, Jeff
• Chen, Zhong

• thermal noise
• noise performance
• LNA
• power consumption
• parasitic resistances
• SpectreRF
• Electrical and Electronics
• Power and Energy
• Signal Processing
• Systems and Communications

Repository record dc:identifier

https://scholarworks.uark.edu/etd/3598

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-5129