Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.
While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm.
This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in circuit type, circuit scale, and technology node, including 130 nm, 90 nm, and 45 nm processes. These results are compared with synchronous counterparts and analyzed for a range of trends in order to identify and quantify advantages and disadvantages of NCL across a variety of applications. By providing an evaluation of a broad range of circuits and characteristics, an IC designer may effectively predict the advantages or disadvantages of an NCL implementation for their application.
","abstract_html":"<p>Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness. </p> <p>While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm. </p> <p>This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in circuit type, circuit scale, and technology node, including 130 nm, 90 nm, and 45 nm processes. These results are compared with synchronous counterparts and analyzed for a range of trends in order to identify and quantify advantages and disadvantages of NCL across a variety of applications. By providing an evaluation of a broad range of circuits and characteristics, an IC designer may effectively predict the advantages or disadvantages of an NCL implementation for their application. </p>","abstract_has_math":false,"creators":["Brady, John Davis"],"institution":null,"degree_name":"Doctor of Philosophy in Engineering (PhD)","degree_level":"Dissertation","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Parkerson, James P.","Thompson, Dale R."],"advisors":["Di, Jia"],"committee_chairs":[],"committee_members":[],"year":2019,"date_issued":"2019-12-01T08:00:00Z","date_published":"2019-12-01T08:00:00Z","updated_at":"2026-07-24T00:59:01Z","subjects":["Asynchronous Energy Consumption","Asynchronous IC Design","Asynchronous Power Consumption","NULL Convention Logic","Static Power Consumption","Voltage Scaling","Digital Circuits","Power and Energy","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/3466","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Parkerson, James P.","Thompson, Dale R."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Di, Jia"]},{"key":"dc:creator","label":"Author","values":["Brady, John Davis"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2019"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2024-02-06T08:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy in Engineering (PhD)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["Asynchronous Energy Consumption","Asynchronous IC Design","Asynchronous Power Consumption","NULL Convention Logic","Static Power Consumption","Voltage Scaling","Digital Circuits","Power and Energy","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/3466"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["Integrated circuit (IC) designers face many challenges in utilizing state-of-the-art technology nodes, such as the increased effects of process variation on timing analysis and heterogeneous multi-die architectures that span across multiple technologies while simultaneously increasing performance and decreasing power consumption. These challenges provide opportunity for utilization of asynchronous design paradigms due to their inherent flexibility and robustness.
While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm.
This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in circuit type, circuit scale, and technology node, including 130 nm, 90 nm, and 45 nm processes. These results are compared with synchronous counterparts and analyzed for a range of trends in order to identify and quantify advantages and disadvantages of NCL across a variety of applications. By providing an evaluation of a broad range of circuits and characteristics, an IC designer may effectively predict the advantages or disadvantages of an NCL implementation for their application.
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While NULL Convention Logic (NCL) has been implemented in a variety of applications, current literature does not fully encompass the intricacies of NCL power performance across a variety of applications, technology nodes, circuit scale, and voltage scaling, thereby preventing further adoption and utilization of this design paradigm.
This dissertation evaluates the nominal dynamic energy, voltage-scaled dynamic energy, and static power consumption of NCL across variations in circuit type, circuit scale, and technology node, including 130 nm, 90 nm, and 45 nm processes. These results are compared with synchronous counterparts and analyzed for a range of trends in order to identify and quantify advantages and disadvantages of NCL across a variety of applications. By providing an evaluation of a broad range of circuits and characteristics, an IC designer may effectively predict the advantages or disadvantages of an NCL implementation for their application.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/3466"],"dc:subject":["Asynchronous Energy Consumption","Asynchronous IC Design","Asynchronous Power Consumption","NULL Convention Logic","Static Power Consumption","Voltage Scaling","Digital Circuits","Power and Energy","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["Evaluation and Analysis of NULL Convention Logic Circuits"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Doctor of Philosophy in Engineering (PhD)"]},"updated_at":"2026-07-24T00:59:01Z"}