This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology.
","abstract_html":"<p>This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology. </p>","abstract_has_math":false,"creators":["Sabado, Francis Corpuz"],"institution":null,"degree_name":"Doctor of Philosophy in Engineering (PhD)","degree_level":"Dissertation","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Thompson, Dale R.","Parkerson, James P."],"advisors":["Di, Jia"],"committee_chairs":[],"committee_members":[],"year":2017,"date_issued":"2017-12-01T08:00:00Z","date_published":"2017-12-01T08:00:00Z","updated_at":"2026-07-24T00:59:49Z","subjects":["3D IC","Asynchronous","Integrated Circuit","MTNCL","NCL","Three-dimensional","Computer Sciences","Electrical and Electronics","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/2584","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Thompson, Dale R.","Parkerson, James P."]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Di, Jia"]},{"key":"dc:creator","label":"Author","values":["Sabado, Francis Corpuz"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date","label":"Dc Date","values":["2017"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2024-02-06T08:00:00Z"]},{"key":"thesis:degree_level","label":"Degree Level","values":["Dissertation"]},{"key":"thesis:degree_name","label":"Degree Name","values":["Doctor of Philosophy in Engineering (PhD)"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["3D IC","Asynchronous","Integrated Circuit","MTNCL","NCL","Three-dimensional","Computer Sciences","Electrical and Electronics","VLSI and Circuits, Embedded and Hardware Systems"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://scholarworks.uark.edu/etd/2584"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology.
"]},{"key":"dc:title","label":"Title","values":["Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits"]}]}],"canonical_facts":{"dc:contributor":["Thompson, Dale R.","Parkerson, James P."],"dc:contributor.advisor":["Di, Jia"],"dc:creator":["Sabado, Francis Corpuz"],"dc:date":["2017"],"dc:date.available":["2024-02-06T08:00:00Z"],"dc:description.abstract":["This dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs were implement in NCL, MTNCL, and synchronous architecture to compare synchronous and asynchronous circuits in 2D and 3D ICs. The designs were normalized based on performance and several metrics were measured for comparison. Area, interconnect length, power consumption, and power density were compared among NCL, MTNCL, and synchronous designs. The NCL and MTNCL designs showed improvements in all metrics when moving from 2D to 3D. The 3D NCL and MTNCL designs also showed a balanced power distribution in post-layout analysis. This could alleviate the hotspot problem prevalently found in most 3D ICs. NCL and MTNCL have the potential to synergize well with 3D IC technology.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/2584"],"dc:subject":["3D IC","Asynchronous","Integrated Circuit","MTNCL","NCL","Three-dimensional","Computer Sciences","Electrical and Electronics","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits"],"thesis:degree_level":["Dissertation"],"thesis:degree_name":["Doctor of Philosophy in Engineering (PhD)"]},"updated_at":"2026-07-24T00:59:49Z"}