A novel reconfigurable digital-to-analog converter (DAC) with supply independent linearity is presented. The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog \"summing\" core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable signal. Supply independence is achieved through the use of a charge-based approach in the analog core utilizing a finite stepping voltage derived from another, much smaller, voltage reference. This voltage reference in turn determines the resolution of the DAC. The DAC will thus create a \"stair-stepping\" analog output until digital input is met or the voltage supply is reached. Feedback is utilized when either of these events occurs notifying the DAC to wait until another sample is requested. Low power is achieved by using static CMOS logic and the inclusion of a \"sleep mode\" in the analog core which can be used after the desired output is achieved. This design was implemented across two different processes with different power supplies to confirm the architecture.
","abstract_html":"<p>A novel reconfigurable digital-to-analog converter (DAC) with supply independent linearity is presented. The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog "summing" core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable signal. Supply independence is achieved through the use of a charge-based approach in the analog core utilizing a finite stepping voltage derived from another, much smaller, voltage reference. This voltage reference in turn determines the resolution of the DAC. The DAC will thus create a "stair-stepping" analog output until digital input is met or the voltage supply is reached. Feedback is utilized when either of these events occurs notifying the DAC to wait until another sample is requested. Low power is achieved by using static CMOS logic and the inclusion of a "sleep mode" in the analog core which can be used after the desired output is achieved. This design was implemented across two different processes with different power supplies to confirm the architecture.</p>","abstract_has_math":false,"creators":["Chiolino, Nicholas J."],"institution":null,"degree_name":"Master of Science in Electrical Engineering (MSEE)","degree_level":"Thesis","degree_discipline":null,"degree_department":null,"school":null,"contributors":["Brown, Randy L.","Di, Jia"],"advisors":["Mantooth, H. Alan"],"committee_chairs":[],"committee_members":[],"year":2013,"date_issued":"2013-12-01T08:00:00Z","date_published":"2013-12-01T08:00:00Z","updated_at":"2026-07-24T01:00:19Z","subjects":["Applied sciences","Data converters","Digital to analog converters","Integrated circuit","Low power","Ramp generator","Switch capacitor","Electrical and Electronics","VLSI and Circuits, Embedded and Hardware Systems"],"languages":[],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://scholarworks.uark.edu/etd/993","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Brown, Randy L.","Di, Jia"]},{"key":"dc:contributor.advisor","label":"Advisor","values":["Mantooth, H. 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The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog \"summing\" core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable signal. Supply independence is achieved through the use of a charge-based approach in the analog core utilizing a finite stepping voltage derived from another, much smaller, voltage reference. This voltage reference in turn determines the resolution of the DAC. The DAC will thus create a \"stair-stepping\" analog output until digital input is met or the voltage supply is reached. Feedback is utilized when either of these events occurs notifying the DAC to wait until another sample is requested. Low power is achieved by using static CMOS logic and the inclusion of a \"sleep mode\" in the analog core which can be used after the desired output is achieved. This design was implemented across two different processes with different power supplies to confirm the architecture.
"]},{"key":"dc:title","label":"Title","values":["A Reconfigurable Digital-to-Analog Converter with Supply Invariant Linearity"]}]}],"canonical_facts":{"dc:contributor":["Brown, Randy L.","Di, Jia"],"dc:contributor.advisor":["Mantooth, H. Alan"],"dc:creator":["Chiolino, Nicholas J."],"dc:date":["2013"],"dc:date.available":["2017-09-29T07:00:00Z"],"dc:description.abstract":["A novel reconfigurable digital-to-analog converter (DAC) with supply independent linearity is presented. The process agnostic converter achieves wide supply range operation and re-configurability by being charge based. This converter consists of a 7-bit parallel digital input control core and an analog \"summing\" core utilizing charging capacitors with an operational transconductance amplifier in a voltage-follower configuration. This topology is highly configurable to allow for optimization across process voltages, step sizes and low power operation. The specification of the DAC is (1) supply independence (2) low power operation (3) operation up to 200 kHz and (4) conversion control through a DAC enable signal. Supply independence is achieved through the use of a charge-based approach in the analog core utilizing a finite stepping voltage derived from another, much smaller, voltage reference. This voltage reference in turn determines the resolution of the DAC. The DAC will thus create a \"stair-stepping\" analog output until digital input is met or the voltage supply is reached. Feedback is utilized when either of these events occurs notifying the DAC to wait until another sample is requested. Low power is achieved by using static CMOS logic and the inclusion of a \"sleep mode\" in the analog core which can be used after the desired output is achieved. This design was implemented across two different processes with different power supplies to confirm the architecture.
"],"dc:identifier":["https://scholarworks.uark.edu/etd/993"],"dc:subject":["Applied sciences","Data converters","Digital to analog converters","Integrated circuit","Low power","Ramp generator","Switch capacitor","Electrical and Electronics","VLSI and Circuits, Embedded and Hardware Systems"],"dc:title":["A Reconfigurable Digital-to-Analog Converter with Supply Invariant Linearity"],"thesis:degree_level":["Thesis"],"thesis:degree_name":["Master of Science in Electrical Engineering (MSEE)"]},"updated_at":"2026-07-24T01:00:19Z"}