Design and Analysis of an Adaptive Asynchronous System Architecture for Energy Efficiency

<p>Power has become a critical design parameter for digital CMOS integrated circuits. With performance still garnering much concern, a central idea has emerged: minimizing power consumption while maintaining performance. The use of dynamic voltage scaling (DVS) with parallelism has shown to be an effective way of saving power while maintaining performance. However, the potency of DVS and parallelism in traditional, clocked synchronous systems is limited because of the strict timing requirements such systems must comply with. Delay-insensitive (DI) asynchronous systems have the potential to benefit more from these techniques due to their flexible timing requirements and high modularity. This dissertation presents the design and analysis of a real-time adaptive DVS architecture for paralleled Multi-Threshold NULL Convention Logic (MTNCL) systems. Results show that energy-efficient systems with low area overhead can be created using this approach.</p>

Name thesis:degree_name

Doctor of Philosophy in Engineering (PhD)

Level thesis:degree_level

Dissertation

Year dc:date.available

2012

Author dc:creator

• Hollosi, Brent Michael

Advisor dc:contributor.advisor

• Di, Jia

Contributors dc:contributor

• Mantooth, H. Alan
• Smith, Scott C.

• Applied sciences
• Adaptive asynchronous architecture
• Asynchronous
• Digital
• Energy efficiency
• Ncl
• Electrical and Electronics
• Systems and Communications
• VLSI and Circuits, Embedded and Hardware Systems

Repository record dc:identifier

https://scholarworks.uark.edu/etd/654

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-1653