Thermal and Electrical Parasitic Modeling for Multi-Chip Power Module Layout Synthesis

<p><strong>This thesis presents thermal and electrical parasitic modeling approaches for layout synthesis of Multi-Chip Power Modules (MCPMs). MCPMs integrate power semiconductor devices and drive electronics into a single package. As the switching frequency of power devices increases, the size of the passive components are greatly reduced leading to gains in efficiency and cost reduction. In order to increase switching frequency, electrical parasitics in MCPMs need to be reduced through tighter electronic integrations and smaller packages. As package size is decreased, temperature increases due to less heat dissipation capability. Thus, it is crucial to consider both thermal and electrical parasitics in order to avoid premature device failure. Traditionally, the evaluation of the temperature and electrical parasitics of an MCPM requires the layout to be changed iteratively by hand and verified via finite element analysis (FEA) tools. The novel thermal and electrical parasitics models developed in this thesis predict temperature and electrical parasitics of an MCPM according to varied layouts. Multi-Objective optimization methods are applied to the models to find optimal layouts and tradeoffs of MCPM layouts.</strong></p>

Name thesis:degree_name

Master of Science in Electrical Engineering (MSEE)

Level thesis:degree_level

Thesis

Year dc:date.available

2012

Author dc:creator

• Gong, Zihao

Advisor dc:contributor.advisor

• Mantooth, H. Alan

Contributors dc:contributor

• Brown, Randy L.
• Balda, Juan C.

• Applied sciences
• Electrical parasitics
• Multi-chip power module
• Thermal modeling
• Electrical and Electronics
• Power and Energy

Repository record dc:identifier

https://scholarworks.uark.edu/etd/635

OAI identifier oai:identifier

oai:scholarworks.uark.edu:etd-1634