Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
type: CreativeWork
description: The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integra…
abstract: The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integra…
author: Jung, Seok Min
language: en_US
keywords: Digitally Controlled Oscillator, Digital Phase-locked Loop, Feedback Voltage-controlled Oscillator, Phase Interpolator, Radiation-hardened-by-design, Electrical & Computer Engineering, Adaptive-bandwidth
date published: 2016
date modified: 2026-07-24T00:57:45Z
provider: University of Arizona
publisher: Networked Digital Library of Theses and Dissertations
type: WebPage
source organization: The University of Arizona.

PropertyValue
property ID: Handle
value: http://hdl.handle.net/10150/621292