III-V compound semiconductor integrated charge storage structures for dynamic and non-volatile memory elements.

This thesis presents an investigation into a novel group of GaAs charge storage devices. These devices, which are an integration of bipolar and junction field effect transistor structures were conceived, designed, fabricated, and tested within this study. The purpose was to analyse new types of charge storage devices, which are suitable for fabrication and lead to the development of dynamic and nonvolatile memories in III-V compound semiconductors. Currently, III-V semiconductor storage devices consist only of capacitors, where data is destroyed during reading and electrical erasure is difficult. In this work, four devices types were demonstrated that exhibit nondestructive reading, and three of the prototypes can be electrically erased. All types use the junction field effect transistor (JFET) for charge sensing, with each having different bipolar or epitaxial layer structure controlling the junction gate. The bottom epitaxial layer in each case served as the JFET channel. Two of the device types have three alternately doped layers, while the remaining two have four alternately doped layers. In all cases, removal of majority carriers from the middle layers constitutes stored charge. The missing carriers deplete the current carrying a region of the JFET channel. Drain current of the JFET becomes an indicator of stored charge. The basic function of each JFET memory element type is independent of interchanging n- and p- type doping within the structure type. Some performance advantage can be realized, however, by sensing with an n-type channel as compared to p- type due to increased carrier mobility. All device types exhibit storage time characteristics of order ten seconds. Devices are constructed in epitaxial layers grown by molecular beam epitaxy (MBE) reactors. The design of the epitaxial layers is an intrinsic part, together with the electrical design, of the storage device concept. These concepts are implemented first with photolithography masks which are used in device fabrication. The fabrication methods employ wet chemical etching and ohmic metal liftoff techniques. Electrical dc and charge retention time characteristics along with functionality read/write operations for the memory element group are measured using commercial electronic test equipment.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

doctoral

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Grantor dc:publisher

The University of Arizona.

Year dc:date.issued

1992

Author dc:creator

• Hetherington, Dale Laird.

Committee member dc:contributor.committeemember

• Galloway, Kenneth F.

• Dissertations, Academic.
• Electrical engineering.
• Condensed matter.

Statement dc:rights

• Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.

Language dc:language.iso

en

Handle dc:identifier.uri

http://hdl.handle.net/10150/186112

OAI identifier oai:identifier

oai:repository.arizona.edu:10150/186112