A Comparative Analysis of Experimental and Computational Methods for Evaluating Partial Discharge Inception Voltage on Printed Circuit Boards
Partial discharge (PD) presents a significant reliability concern in medium-voltage (MV) and high-voltage (HV) systems, particularly as power electronics applications continue to push to higher voltage levels. One aspect of MV/HV system design that has not received much treatment in the literature pertains to the design of printed circuit boards (PCBs) for these voltage levels. This thesis investigates the likelihood of PD behavior in HV PCBs and evaluates the suitability of existing design guidance for avoiding this behavior in the implementation of HV PCBs. As part of this analysis, five PCB test subjects were designed and evaluated using both experimental procedures and finite-element (FE) simulations. Experimental measurements were conducted using a standard-based 60 Hz AC voltage stimulus to determine the partial discharge inception voltage (PDIV) for each design. Simulations of the geometry for each PCB test subject were also conducted using COMSOL Multiphysics. The resulting FE models were analyzed using two techniques: a traditional maximum-field-based approach and a newly-proposed critical-area integration method. This new metric provides a promising approach to aid future designs after experimental calibration. This outcome makes the critical area method a potential candidate for predictive modeling to prevent PD in MV/HV PCB design.
Finite-Element Simulation, High-Voltage, Partial Discharge, Partial Discharge Inception Voltage, PCBs, Printed Circuit Boards
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