Equivalent Modeling of Medium-Voltage Gate Drive Circuitry

There has been a recent increase in the utilization of wide bandgap (WBG) devices in power electronic converter designs. Designs leveraging these devices are capable of achieving high efficiencies and increased power density as compared to more traditional Silicon (Si) based converters. The same behaviors responsible for the increase in utilization of WBG devices also cause an increase in electromagnetic interference (EMI) and potential false turn-on events. The high edge rates for the devices can induce significant current through the gate-to-drain capacitor, causing disturbance voltages across the gate-to-source nodes. The gate-to-source voltage controls whether the device turns on or off, and the disturbance voltages can be severe enough to cause shoot through or even cause the device to fail. Additionally, the more spectrally rich profiles for WBG devices creates challenges for common-mode (CM) conducted emissions behavior that can also negatively affect the gate drive design. This dissertation leverages a decomposition technique to derive equivalent models for the differential-mode (DM) and CM behavior for a medium voltage gate driver. A set of DM and CM templates for a generalized two-line system are leveraged with a design procedure to resolve the equivalent models. These models are then mathematically validated in a state-space simulation environment across a wide range of parameter values. Once validated, the models are then analyzed to identify influential parameters that can potentially disrupt the gate-to-source voltage for the high-side switching device. Specifically, the device capacitor network and gate resistor asymmetry are shown to be highly sensitive parameters for the gate-to-source voltage disturbance. The equivalent models are then validated on an empirical evaluation platform across a broad range of configurations. Additionally, a set of empirical studies are carried out to validate the predicted behavior provided in the analysis. The device capacitor ratio has been previously shown to be a sensitive parameter for the gate-to-source voltage, and this is reaffirmed in the empirical studies. The influence of the gate resistors is a unique behavior solely identified by leveraging the DM and CM equivalent models. The gate resistor asymmetry is shown to be a parameter that can be leveraged to increase the reliability of a gate drive design in an otherwise susceptible configuration. Specifically, placing all or most of the gate resistance at the gate node significantly improves the reliability of the gate drive design.

Grantor dc:publisher

University of Alabama Libraries

Year dc:date.issued

2023

Author dc:creator

• Helton, Jared

Advisor dc:contributor.advisor

• Lemmon, Andrew N

Contributors dc:contributor

• Abu Qahouq, Jaber
• Baker, Nicholas
• Beechner, Troy
• Brovont, Aaron
• Freeborn, Todd

• Common-mode
• Conducted Emissions
• Differential-Mode
• Electromagnetic Interference
• False Turn-On
• Gate Drive

Statement dc:rights

• All rights reserved by the author unless otherwise indicated.

Language dc:language.iso

en_US, English

Dc Identifier Other

1028521

OAI identifier oai:identifier

oai:ir.ua.edu:123456789/13176