Design of an IEEE double precision floating-point adder/subtractor in GaAs technology

This project aims to produce a 64-bit floating-point double precision adder/subtractor of a Solid Modelling accelerator in Gallium Arsenide technology, which is used to reduce computational time and to increase accuracy of algorithms. Addition is the most fundamental and the simplest operation in any computer arithmetic operation. According to the IEEE 754 Standard Format, the resulting architecture based on the addition/subtraction algorithm is mainly divided into two portions - the exponent and the mantissa. In logic design, there are three major difficult circuits including a mantissa shifter, a mantissa adder, and a normalizer, all of which affect the speed of the addition process. Design of a high speed operation not only relies on speed property of a gate, an efficient way to accelerate the process but also is on selection and design of the fastest feasible circuits, and an optimal placement to reduce interconnections. A rapid barrel shifter has been used as an alignment shifter and a normalization shifter, and an adder combined a carry-select adder and a binary carry-look ahead adder has been developed for adding the two mantissas. In normalization, a novel approach has been adopted while designing the encoder, which omits the 6-bit incrementer normally required in this process. As a result of the idiosyncrasies of GaAs technology, the design is much more difficult than CMOS. For simplicity of layout, a multi-bit-input circuit has been broken into several segments, then connected together to achieve the desired function. Furthermore, some examples of PLA implementation are given in the priority detector and the encoder.

Author dc:creator

• Liu, Qiong

Advisor dc:contributor.advisor

• Liebelt, Michael

Language dc:language.iso

en

Handle dc:identifier.uri

http://hdl.handle.net/2440/122410

OAI identifier oai:identifier

oai:digital.library.adelaide.edu.au:2440/122410