{"id":{"repo_id":"aalto","oai_identifier":"oai:aaltodoc.aalto.fi:123456789/2649"},"canonical_url":"https://search.dev.ndltd.org/etd/aalto/oai:aaltodoc.aalto.fi:123456789/2649","repository":{"repo_id":"aalto","name":"Aalto University","base_url":"https://aaltodoc.aalto.fi/server/oai/request"},"display":{"title":"Analog parallel processor solutions for video encoding","abstract":"This thesis deals with Cellular Nonlinear Network (CNN) analog parallel processor networks and their implementations in current video coding standards. The target applications are low-power video encoders within 3rd generation mobile terminals. The video codecs of such mobile terminals are defined by either the MPEG-4/H.263 or H.264 video standard. All of these standards are based on the block-based hybrid approach. As block-based motion estimation (ME) is responsible for most of the power consumption of such hybrid video encoders, this thesis deals mostly with low-power ME implementations. Low-power solutions are introduced at both the algorithmic and hardware levels. On the algorithmic level, the introduced implementations are derived from a segmentation algorithm, which has previously been partly realized. The first introduced algorithm reduces the computational complexity of ME within an object-based MPEG-4 encoder. The use of this algorithm enables a 60% drop in the power consumption of Full Search ME. The second algorithm calculates a near-optimal block-size partition for H.264 motion estimation. With this algorithm, the use of computationally complex Lagrange optimization in H.264 ME is not required. The third algorithm reduces the shape bit-rate of an object-based MPEG-4 encoder. On the hardware level a CNN-type ME architecture is introduced. The architecture includes connections and circuitry to fully realize block-based ME. The analog ME implemented with this architecture is capable of lower power than comparable digital realizations. A 9×9 test chip has also been realized. Additionally implemented is a digital predictive ME realization that takes advantage of the introduced partition algorithm. Although the IC layout of the ME algorithm was drawn, the design was verified as an FPGA.","abstract_html":"This thesis deals with Cellular Nonlinear Network (CNN) analog parallel processor networks and their implementations in current video coding standards. The target applications are low-power video encoders within 3rd generation mobile terminals. The video codecs of such mobile terminals are defined by either the MPEG-4/H.263 or H.264 video standard. All of these standards are based on the block-based hybrid approach. As block-based motion estimation (ME) is responsible for most of the power consumption of such hybrid video encoders, this thesis deals mostly with low-power ME implementations. Low-power solutions are introduced at both the algorithmic and hardware levels. On the algorithmic level, the introduced implementations are derived from a segmentation algorithm, which has previously been partly realized. The first introduced algorithm reduces the computational complexity of ME within an object-based MPEG-4 encoder. The use of this algorithm enables a 60% drop in the power consumption of Full Search ME. The second algorithm calculates a near-optimal block-size partition for H.264 motion estimation. With this algorithm, the use of computationally complex Lagrange optimization in H.264 ME is not required. The third algorithm reduces the shape bit-rate of an object-based MPEG-4 encoder. On the hardware level a CNN-type ME architecture is introduced. The architecture includes connections and circuitry to fully realize block-based ME. The analog ME implemented with this architecture is capable of lower power than comparable digital realizations. A 9×9 test chip has also been realized. Additionally implemented is a digital predictive ME realization that takes advantage of the introduced partition algorithm. Although the IC layout of the ME algorithm was drawn, the design was verified as an FPGA.","abstract_has_math":false,"creators":["Koskinen, Lauri"],"institution":"Helsinki University of Technology","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":"Department of Electrical and Communications Engineering","school":null,"contributors":["Aalto-yliopisto","Aalto University"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2005,"date_issued":"2005-12-16","date_published":"2005-12-16","updated_at":"2026-07-27T18:39:42Z","subjects":[],"languages":["en"],"rights":[],"rights_urls":[],"identifier_entries":[]},"links":{"outbound_url":"https://aaltodoc.aalto.fi/handle/123456789/2649","outbound_label":"Repository record","outbound_source":"dc:identifier.uri"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Aalto-yliopisto","Aalto University"]},{"key":"dc:contributor.department","label":"Department","values":["Department of Electrical and Communications Engineering","Sähkö- ja tietoliikennetekniikan osasto"]},{"key":"dc:creator","label":"Author","values":["Koskinen, Lauri"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:date.accessioned","label":"Dc Date Accessioned","values":["2012-02-17T07:26:27Z"]},{"key":"dc:date.available","label":"Dc Date Available","values":["2012-02-17T07:26:27Z"]},{"key":"dc:date.issued","label":"Date","values":["2005-12-16"]},{"key":"dc:publisher","label":"Institution","values":["Helsinki University of Technology","Teknillinen korkeakoulu"]},{"key":"dc:type","label":"Dc Type","values":["G4 Monografiaväitöskirja"]},{"key":"dc:type.dcmitype","label":"Dc Type Dcmitype","values":["text"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language.iso","label":"Language (ISO)","values":["en"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier.uri","label":"Identifier URI","values":["https://aaltodoc.aalto.fi/handle/123456789/2649"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description.abstract","label":"Abstract","values":["This thesis deals with Cellular Nonlinear Network (CNN) analog parallel processor networks and their implementations in current video coding standards. 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With this algorithm, the use of computationally complex Lagrange optimization in H.264 ME is not required. The third algorithm reduces the shape bit-rate of an object-based MPEG-4 encoder. On the hardware level a CNN-type ME architecture is introduced. The architecture includes connections and circuitry to fully realize block-based ME. The analog ME implemented with this architecture is capable of lower power than comparable digital realizations. A 9×9 test chip has also been realized. Additionally implemented is a digital predictive ME realization that takes advantage of the introduced partition algorithm. Although the IC layout of the ME algorithm was drawn, the design was verified as an FPGA."]},{"key":"dc:format.mimetype","label":"Dc Format Mimetype","values":["application/pdf"]},{"key":"dc:title","label":"Title","values":["Analog parallel processor solutions for video encoding"]}]}],"canonical_facts":{"dc:contributor":["Aalto-yliopisto","Aalto University"],"dc:contributor.department":["Department of Electrical and Communications Engineering","Sähkö- ja tietoliikennetekniikan osasto"],"dc:creator":["Koskinen, Lauri"],"dc:date.accessioned":["2012-02-17T07:26:27Z"],"dc:date.available":["2012-02-17T07:26:27Z"],"dc:date.issued":["2005-12-16"],"dc:description.abstract":["This thesis deals with Cellular Nonlinear Network (CNN) analog parallel processor networks and their implementations in current video coding standards. The target applications are low-power video encoders within 3rd generation mobile terminals. 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The third algorithm reduces the shape bit-rate of an object-based MPEG-4 encoder. On the hardware level a CNN-type ME architecture is introduced. The architecture includes connections and circuitry to fully realize block-based ME. The analog ME implemented with this architecture is capable of lower power than comparable digital realizations. A 9×9 test chip has also been realized. Additionally implemented is a digital predictive ME realization that takes advantage of the introduced partition algorithm. Although the IC layout of the ME algorithm was drawn, the design was verified as an FPGA."],"dc:format.mimetype":["application/pdf"],"dc:identifier.uri":["https://aaltodoc.aalto.fi/handle/123456789/2649"],"dc:language.iso":["en"],"dc:publisher":["Helsinki University of Technology","Teknillinen korkeakoulu"],"dc:title":["Analog parallel processor solutions for video encoding"],"dc:type":["G4 Monografiaväitöskirja"],"dc:type.dcmitype":["text"]},"updated_at":"2026-07-27T18:39:42Z"}