{"id":{"repo_id":"aachen","oai_identifier":"oai:publications.rwth-aachen.de:62949"},"canonical_url":"https://search.dev.ndltd.org/etd/aachen/oai:publications.rwth-aachen.de:62949","repository":{"repo_id":"aachen","name":"RWTH Aachen University","base_url":"https://publications.rwth-aachen.de/oai2d"},"display":{"title":"Strained and unstrained silicon nanowire array MOSFETs : fabrication and physical analysis","abstract":"Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers pushing the conventional MOSFET electronics towards nanoelectronics. The International Technology Roadmap for Semiconductors (ITRS) predicts the 18nm node for the year 2018, that requires a physical gate length of 7nm or less. It has been widely accepted that the path for the next decades is going to be far more demanding. This includes the introduction of new device concepts (e.g. nanowire or FinFETs), complex material engineering (e.g. III-V, strain engineering) and handling the variability of devices (e.g. random dopant fluctuation, line-edge roughness) as channels approach atomic scales. This thesis investigates the application of NWs as an alternative to conventional planar MOSFETs. For this the following imminent physical and material challenges are examined: i) fabrication and characterization of multi-gate MOSFETs employing top-down fabricated Si nanowire arrays, ii) adaption of strained Si as a high mobility channel material for NW-array MOSFETs, iii) the implementation of Ni silicide S/D contacts for reduced contact resistance and improved carrier injection and iv) transport of charges in single Si NWs during Kelvin Probe Force Microscopy. The multi-gate device architecture is an innovative transistor concept which includes double-gate MOSFETs, Fin-field effect transistors (FinFETs), -gated MOSFETs and gate-all-around MOSFETs. They represent a potential solution to the ongoing reduction of gate length and lower power supply in today's devices. Most of these devices are adapted on silicon-on-insulator (SOI) substrates. By taking a closer look it is shown that it is not only the intrinsic smallness what makes a nanowire such an appealing and versatile structure, but also its very good electrostatic control of the gate. In order to further improve carrier mobility and by that the drive current, NW-array n-MOSFETs were fabricated on biaxially tensile strained SOI substrates. Lateral strain relaxation through patterning is employed to transform biaxial tensile strain into uniaxial tensile strain along <110> and <100> NWs. Similarly to the unstrained devices I-V characterization yields excellent electrostatic behavior of the devices. It was found that o_-currents of the NW array MOSFETs were independent on the channel orientation and the strain within channel. Low temperature I-V characterization of strained and unstrained NW array n-MOSFETs, at temperatures ranging from 4K to 280K, were performed. The inverse subthreshold swing, S(T), follows the theoretical predicted behavior perfectly. An increase of threshold voltage, Vth(T), with decreasing temperature was observed for strained and unstrained devices, respectively. Nickel-silicide contacts unite low extrinsic resistance and, in combination with dopant segregation, low Schottky barrier heights. For NWs, the silicidation speed decreases with increasing NW cross section, but no difference in silicidation speed of strained and unstrained SOI NWs was found. The results indicate volume diffusion of the silicide along the NWs during the silicidation process. Contact resistivities and the resistivities of doped Si NWs are presented as a function of As+ and BF2 ion implantation dose and cross sectional area of NWs. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. Furthermore, Nickel silicide contacts were successfully implemented in NW-array p-MOSFETs. The silicidation of NWs suffered from a strong variation of the silicide segments in length. The fabricated devices showed ambipolar transfer characteristics, which is explained by a hybrid transistor type that includes conventional and SB-MOSFETs within one NW array, due to the variability of the silicided segment lengths. By introducing NiSi the S/D resistance was reduced compared to conventional NW-array p-MOSFETs. NiSi contacts showed an orientation dependence, resulting in lower S/D resistance for <100> NWs compared to <110>. As a consequence NW p-MOSFETs with <100> channels featured drive currents higher than <110>. Kelvin probe force microscopy is successfully applied to investigate unimplanted top-down fabricated Si NWs. The investigations focus on the question of how transport of majority carriers to the measurement position determines the probed KPFM bias. Measurements on implanted Si pads and unimplanted NWs show a correlation of the probed KPFM bias with the transport of majority carriers from the Al contact via the Si pad and into the Si NW. The built-in potential is successfully verified via the probed KPFM bias for equal-type doped junctions, and with the inversion-energy for different-type doping junctions. Additionally, the structural influence on the probed KPFM bias due to expanded vertical asymmetric electric dipoles is discussed.","abstract_html":"Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers pushing the conventional MOSFET electronics towards nanoelectronics. The International Technology Roadmap for Semiconductors (ITRS) predicts the 18nm node for the year 2018, that requires a physical gate length of 7nm or less. It has been widely accepted that the path for the next decades is going to be far more demanding. This includes the introduction of new device concepts (e.g. nanowire or FinFETs), complex material engineering (e.g. III-V, strain engineering) and handling the variability of devices (e.g. random dopant fluctuation, line-edge roughness) as channels approach atomic scales. This thesis investigates the application of NWs as an alternative to conventional planar MOSFETs. For this the following imminent physical and material challenges are examined: i) fabrication and characterization of multi-gate MOSFETs employing top-down fabricated Si nanowire arrays, ii) adaption of strained Si as a high mobility channel material for NW-array MOSFETs, iii) the implementation of Ni silicide S/D contacts for reduced contact resistance and improved carrier injection and iv) transport of charges in single Si NWs during Kelvin Probe Force Microscopy. The multi-gate device architecture is an innovative transistor concept which includes double-gate MOSFETs, Fin-field effect transistors (FinFETs), -gated MOSFETs and gate-all-around MOSFETs. They represent a potential solution to the ongoing reduction of gate length and lower power supply in today&#x27;s devices. Most of these devices are adapted on silicon-on-insulator (SOI) substrates. By taking a closer look it is shown that it is not only the intrinsic smallness what makes a nanowire such an appealing and versatile structure, but also its very good electrostatic control of the gate. In order to further improve carrier mobility and by that the drive current, NW-array n-MOSFETs were fabricated on biaxially tensile strained SOI substrates. Lateral strain relaxation through patterning is employed to transform biaxial tensile strain into uniaxial tensile strain along &lt;110&gt; and &lt;100&gt; NWs. Similarly to the unstrained devices I-V characterization yields excellent electrostatic behavior of the devices. It was found that o_-currents of the NW array MOSFETs were independent on the channel orientation and the strain within channel. Low temperature I-V characterization of strained and unstrained NW array n-MOSFETs, at temperatures ranging from 4K to 280K, were performed. The inverse subthreshold swing, S(T), follows the theoretical predicted behavior perfectly. An increase of threshold voltage, Vth(T), with decreasing temperature was observed for strained and unstrained devices, respectively. Nickel-silicide contacts unite low extrinsic resistance and, in combination with dopant segregation, low Schottky barrier heights. For NWs, the silicidation speed decreases with increasing NW cross section, but no difference in silicidation speed of strained and unstrained SOI NWs was found. The results indicate volume diffusion of the silicide along the NWs during the silicidation process. Contact resistivities and the resistivities of doped Si NWs are presented as a function of As+ and BF2 ion implantation dose and cross sectional area of NWs. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. Furthermore, Nickel silicide contacts were successfully implemented in NW-array p-MOSFETs. The silicidation of NWs suffered from a strong variation of the silicide segments in length. The fabricated devices showed ambipolar transfer characteristics, which is explained by a hybrid transistor type that includes conventional and SB-MOSFETs within one NW array, due to the variability of the silicided segment lengths. By introducing NiSi the S/D resistance was reduced compared to conventional NW-array p-MOSFETs. NiSi contacts showed an orientation dependence, resulting in lower S/D resistance for &lt;100&gt; NWs compared to &lt;110&gt;. As a consequence NW p-MOSFETs with &lt;100&gt; channels featured drive currents higher than &lt;110&gt;. Kelvin probe force microscopy is successfully applied to investigate unimplanted top-down fabricated Si NWs. The investigations focus on the question of how transport of majority carriers to the measurement position determines the probed KPFM bias. Measurements on implanted Si pads and unimplanted NWs show a correlation of the probed KPFM bias with the transport of majority carriers from the Al contact via the Si pad and into the Si NW. The built-in potential is successfully verified via the probed KPFM bias for equal-type doped junctions, and with the inversion-energy for different-type doping junctions. Additionally, the structural influence on the probed KPFM bias due to expanded vertical asymmetric electric dipoles is discussed.","abstract_has_math":false,"creators":["Habicht, Stefan"],"institution":"Publikationsserver der RWTH Aachen University","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["Mantl, Siegfried"],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2011,"date_issued":"2011","date_published":"2011","updated_at":"2026-07-30T19:43:35Z","subjects":["info:eu-repo/classification/ddc/530","Nanoelektronik","Nanodraht","MOS-FET","Kontaktwiderstand","Physik","Nickel-Silizid","silicide","strained silicon"],"languages":["eng"],"rights":["info:eu-repo/semantics/openAccess"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124422%22"],"render_values":[{"text":"https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124422%22","href":"https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124422%22","code":true}]}]},"links":{"outbound_url":"https://publications.rwth-aachen.de/record/62949","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Mantl, Siegfried"]},{"key":"dc:creator","label":"Author","values":["Habicht, Stefan"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:coverage","label":"Dc Coverage","values":["DE"]},{"key":"dc:date","label":"Dc Date","values":["2011"]},{"key":"dc:publisher","label":"Institution","values":["Publikationsserver der RWTH Aachen University"]},{"key":"dc:relation","label":"Dc Relation","values":["info:eu-repo/semantics/altIdentifier/urn/urn:nbn:de:hbz:82-opus-37428"]},{"key":"dc:type","label":"Dc Type","values":["info:eu-repo/semantics/doctoralThesis","info:eu-repo/semantics/publishedVersion"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["info:eu-repo/classification/ddc/530","Nanoelektronik","Nanodraht","MOS-FET","Kontaktwiderstand","Physik","Nickel-Silizid","silicide","strained silicon"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["eng"]},{"key":"dc:rights","label":"Dc Rights","values":["info:eu-repo/semantics/openAccess"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://publications.rwth-aachen.de/record/62949","https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124422%22"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers pushing the conventional MOSFET electronics towards nanoelectronics. The International Technology Roadmap for Semiconductors (ITRS) predicts the 18nm node for the year 2018, that requires a physical gate length of 7nm or less. It has been widely accepted that the path for the next decades is going to be far more demanding. This includes the introduction of new device concepts (e.g. nanowire or FinFETs), complex material engineering (e.g. III-V, strain engineering) and handling the variability of devices (e.g. random dopant fluctuation, line-edge roughness) as channels approach atomic scales. This thesis investigates the application of NWs as an alternative to conventional planar MOSFETs. For this the following imminent physical and material challenges are examined: i) fabrication and characterization of multi-gate MOSFETs employing top-down fabricated Si nanowire arrays, ii) adaption of strained Si as a high mobility channel material for NW-array MOSFETs, iii) the implementation of Ni silicide S/D contacts for reduced contact resistance and improved carrier injection and iv) transport of charges in single Si NWs during Kelvin Probe Force Microscopy. The multi-gate device architecture is an innovative transistor concept which includes double-gate MOSFETs, Fin-field effect transistors (FinFETs), -gated MOSFETs and gate-all-around MOSFETs. They represent a potential solution to the ongoing reduction of gate length and lower power supply in today's devices. Most of these devices are adapted on silicon-on-insulator (SOI) substrates. By taking a closer look it is shown that it is not only the intrinsic smallness what makes a nanowire such an appealing and versatile structure, but also its very good electrostatic control of the gate. In order to further improve carrier mobility and by that the drive current, NW-array n-MOSFETs were fabricated on biaxially tensile strained SOI substrates. Lateral strain relaxation through patterning is employed to transform biaxial tensile strain into uniaxial tensile strain along <110> and <100> NWs. Similarly to the unstrained devices I-V characterization yields excellent electrostatic behavior of the devices. It was found that o_-currents of the NW array MOSFETs were independent on the channel orientation and the strain within channel. Low temperature I-V characterization of strained and unstrained NW array n-MOSFETs, at temperatures ranging from 4K to 280K, were performed. The inverse subthreshold swing, S(T), follows the theoretical predicted behavior perfectly. An increase of threshold voltage, Vth(T), with decreasing temperature was observed for strained and unstrained devices, respectively. Nickel-silicide contacts unite low extrinsic resistance and, in combination with dopant segregation, low Schottky barrier heights. For NWs, the silicidation speed decreases with increasing NW cross section, but no difference in silicidation speed of strained and unstrained SOI NWs was found. The results indicate volume diffusion of the silicide along the NWs during the silicidation process. Contact resistivities and the resistivities of doped Si NWs are presented as a function of As+ and BF2 ion implantation dose and cross sectional area of NWs. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. Furthermore, Nickel silicide contacts were successfully implemented in NW-array p-MOSFETs. The silicidation of NWs suffered from a strong variation of the silicide segments in length. The fabricated devices showed ambipolar transfer characteristics, which is explained by a hybrid transistor type that includes conventional and SB-MOSFETs within one NW array, due to the variability of the silicided segment lengths. By introducing NiSi the S/D resistance was reduced compared to conventional NW-array p-MOSFETs. NiSi contacts showed an orientation dependence, resulting in lower S/D resistance for <100> NWs compared to <110>. As a consequence NW p-MOSFETs with <100> channels featured drive currents higher than <110>. Kelvin probe force microscopy is successfully applied to investigate unimplanted top-down fabricated Si NWs. The investigations focus on the question of how transport of majority carriers to the measurement position determines the probed KPFM bias. Measurements on implanted Si pads and unimplanted NWs show a correlation of the probed KPFM bias with the transport of majority carriers from the Al contact via the Si pad and into the Si NW. The built-in potential is successfully verified via the probed KPFM bias for equal-type doped junctions, and with the inversion-energy for different-type doping junctions. Additionally, the structural influence on the probed KPFM bias due to expanded vertical asymmetric electric dipoles is discussed."]},{"key":"dc:source","label":"Dc Source","values":["Aachen : Publikationsserver der RWTH Aachen University V, 148 S. : Ill., graph. Darst. (2011). = Aachen, Techn. Hochsch., Diss., 2011"]},{"key":"dc:title","label":"Title","values":["Strained and unstrained silicon nanowire array MOSFETs : fabrication and physical analysis"]}]}],"canonical_facts":{"dc:contributor":["Mantl, Siegfried"],"dc:coverage":["DE"],"dc:creator":["Habicht, Stefan"],"dc:date":["2011"],"dc:description":["Today, state of the art MOSFETs feature effective gate lengths of only a few tens of nanometers pushing the conventional MOSFET electronics towards nanoelectronics. The International Technology Roadmap for Semiconductors (ITRS) predicts the 18nm node for the year 2018, that requires a physical gate length of 7nm or less. It has been widely accepted that the path for the next decades is going to be far more demanding. This includes the introduction of new device concepts (e.g. nanowire or FinFETs), complex material engineering (e.g. III-V, strain engineering) and handling the variability of devices (e.g. random dopant fluctuation, line-edge roughness) as channels approach atomic scales. This thesis investigates the application of NWs as an alternative to conventional planar MOSFETs. For this the following imminent physical and material challenges are examined: i) fabrication and characterization of multi-gate MOSFETs employing top-down fabricated Si nanowire arrays, ii) adaption of strained Si as a high mobility channel material for NW-array MOSFETs, iii) the implementation of Ni silicide S/D contacts for reduced contact resistance and improved carrier injection and iv) transport of charges in single Si NWs during Kelvin Probe Force Microscopy. The multi-gate device architecture is an innovative transistor concept which includes double-gate MOSFETs, Fin-field effect transistors (FinFETs), -gated MOSFETs and gate-all-around MOSFETs. They represent a potential solution to the ongoing reduction of gate length and lower power supply in today's devices. Most of these devices are adapted on silicon-on-insulator (SOI) substrates. By taking a closer look it is shown that it is not only the intrinsic smallness what makes a nanowire such an appealing and versatile structure, but also its very good electrostatic control of the gate. In order to further improve carrier mobility and by that the drive current, NW-array n-MOSFETs were fabricated on biaxially tensile strained SOI substrates. Lateral strain relaxation through patterning is employed to transform biaxial tensile strain into uniaxial tensile strain along <110> and <100> NWs. Similarly to the unstrained devices I-V characterization yields excellent electrostatic behavior of the devices. It was found that o_-currents of the NW array MOSFETs were independent on the channel orientation and the strain within channel. Low temperature I-V characterization of strained and unstrained NW array n-MOSFETs, at temperatures ranging from 4K to 280K, were performed. The inverse subthreshold swing, S(T), follows the theoretical predicted behavior perfectly. An increase of threshold voltage, Vth(T), with decreasing temperature was observed for strained and unstrained devices, respectively. Nickel-silicide contacts unite low extrinsic resistance and, in combination with dopant segregation, low Schottky barrier heights. For NWs, the silicidation speed decreases with increasing NW cross section, but no difference in silicidation speed of strained and unstrained SOI NWs was found. The results indicate volume diffusion of the silicide along the NWs during the silicidation process. Contact resistivities and the resistivities of doped Si NWs are presented as a function of As+ and BF2 ion implantation dose and cross sectional area of NWs. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. Furthermore, Nickel silicide contacts were successfully implemented in NW-array p-MOSFETs. The silicidation of NWs suffered from a strong variation of the silicide segments in length. The fabricated devices showed ambipolar transfer characteristics, which is explained by a hybrid transistor type that includes conventional and SB-MOSFETs within one NW array, due to the variability of the silicided segment lengths. By introducing NiSi the S/D resistance was reduced compared to conventional NW-array p-MOSFETs. NiSi contacts showed an orientation dependence, resulting in lower S/D resistance for <100> NWs compared to <110>. As a consequence NW p-MOSFETs with <100> channels featured drive currents higher than <110>. Kelvin probe force microscopy is successfully applied to investigate unimplanted top-down fabricated Si NWs. The investigations focus on the question of how transport of majority carriers to the measurement position determines the probed KPFM bias. Measurements on implanted Si pads and unimplanted NWs show a correlation of the probed KPFM bias with the transport of majority carriers from the Al contact via the Si pad and into the Si NW. The built-in potential is successfully verified via the probed KPFM bias for equal-type doped junctions, and with the inversion-energy for different-type doping junctions. Additionally, the structural influence on the probed KPFM bias due to expanded vertical asymmetric electric dipoles is discussed."],"dc:identifier":["https://publications.rwth-aachen.de/record/62949","https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124422%22"],"dc:language":["eng"],"dc:publisher":["Publikationsserver der RWTH Aachen University"],"dc:relation":["info:eu-repo/semantics/altIdentifier/urn/urn:nbn:de:hbz:82-opus-37428"],"dc:rights":["info:eu-repo/semantics/openAccess"],"dc:source":["Aachen : Publikationsserver der RWTH Aachen University V, 148 S. : Ill., graph. Darst. (2011). = Aachen, Techn. Hochsch., Diss., 2011"],"dc:subject":["info:eu-repo/classification/ddc/530","Nanoelektronik","Nanodraht","MOS-FET","Kontaktwiderstand","Physik","Nickel-Silizid","silicide","strained silicon"],"dc:title":["Strained and unstrained silicon nanowire array MOSFETs : fabrication and physical analysis"],"dc:type":["info:eu-repo/semantics/doctoralThesis","info:eu-repo/semantics/publishedVersion"]},"updated_at":"2026-07-30T19:43:35Z"}