Theory and implementation of digital bang-bang frequency synthesizers for high speed serial communications
In this thesis the theory and implementation of a digital bang-bang frequency synthesizer for application in the field of high speed serial data communications systems is presented. As major building blocks, the synthesizer architecture features a Binary Phase Detector (BPD), a Digital Loop Filter and a Digitally Controlled LC Oscillator (DCO) with a programmable coil in order to cover three different frequency domains. A framework is provided for the nonlinear analysis of the dynamics of the system, based on an analysis of the trajectories of the system in an appropriate phase plane. This approach allowed the derivation of the conditions for stability also in presence of latency in the loop and for input modulation tolerance, and provided insights into the output clock jitter performance. The phase-plane based nonlinear analysis could not be usefully exploited in the presence of jitter on the reference clock and of thermal noise in the synthesizer’s internal blocks, so that a linearized model for the synthesizer has been developed. The linearization of the loop (and in particular of the BPD) has been carried out by using a stochastic approach and by making use of Markov Chain theory. The linearized model has been used to compute the phase transfer function parameters like peaking and bandwidth and the noise generation performances of the synthesizer. Whether the nonlinear model or the linearized one has to be used for the analysis of the synthesizer depends on the amount of noise in the system. A value for this noise threshold has been derived in this work. The architecture proposed has the drawback that the input-output transfer function is dependent on the input jitter. A digital method for the stabilization of the transfer function based on non-parametric estimation has been proposed in this thesis together with a possible implementation form. Throughout the whole work, the analytical approach has been escorted by simulations of synthesizer using software models written in Matlab and in VHDL. The agreement between theory and model is very good for all realistic conditions of operation. A prototype for the synthesizer has been implemented on silicon using a 130nm CMOS technology. The measurements are in very good agreement with the theory and the software models. Outstanding jitter performance of 600fs to 650fs has been measured. This thesis proves that a fully integrated all-digital approach to the low-jitter frequency synthesis is possible also with high bandwidth bang-bang loops in CMOS technology, and that the theory describing the dynamics, jitter generation and jitter tolerance is known to a high degree of accuracy. The results of this work have been published in 4 articles on international journals and conferences (ESSCIRC, ISSCC, IEEE Journal of Solid-State Circuits, IEEE Trans. on Circuits and Systems). A fifth article has been accepted for publication on IEEE Trans. on Circuits and Systems.
info:eu-repo/classification/ddc/620, Phasenregelkreis, Ingenieurwissenschaften, Bang-Bang, Digital, PLL
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