{"id":{"repo_id":"aachen","oai_identifier":"oai:publications.rwth-aachen.de:61396"},"canonical_url":"https://search.dev.ndltd.org/etd/aachen/oai:publications.rwth-aachen.de:61396","repository":{"repo_id":"aachen","name":"RWTH Aachen University","base_url":"https://publications.rwth-aachen.de/oai2d"},"display":{"title":"Verlustleistungs-Modellierung exemplarischer Schlüsselkomponenten der hochratigen digitalen Signalverarbeitung","abstract":"With the continuous exponential growth in complexity and the increasing performance potential of highly integrated CMOS circuits, the power dissipation of such circuits has become one of the most serious design problems. This is not limited to obvious applications, such as hand-held and battery-operated systems or general-purpose-processor based systems, which suffer from a well known, continuously increasing technological challenge due to the energy supply and removal. As well in less obvious applications the power dissipation is often a decisive cost factor. Thus, the power dissipation can have a dramatic influence on the commercial success or can even decide on the realisation of a product due to the necessary choice of an expensive package with a low thermal resistance. Therewith the power dissipation is one of the most important specification parameter which has to be carefully examined during the whole design process and which in case of need has to be minimised in iterative design cycles. With the improvements of simulation techniques today's CAD-tools combine accurate power dissipation values at the physical design level with an acceptable computational effort. But there is a serious lack of concepts for sufficiently accurate power estimation at low computational effort to support the design process on higher system levels. On the other hand the estimation of other parameters, such as the maximum throughput rate and particularly the silicon area is quite simple and is sufficiently well controlled. Therefore, a new concept for power modeling is elaborated and verified in the presented work. Especially for power critical system components in the area of high throughput digital signal processing a physically oriented design flow ensures a highly efficient implementation meeting technological requirements. Therefore, the proposed modeling methodology especially focuses on the constraints and requirements that apply to the power estimation of such highly optimised CMOS-implementations. Based on the structure of the circuit and on the average energy consumptions of the used basic-cells, quite simple arithmetic power models are elaborated which are refined with correction functions. These functions phenomenologically approximate the internal switching activity as a function of the switching activity of the input signals. For the example of transversal filters starting with simple direct form filters, based on atomic components (such as adders and multipliers) to highly optimised filters, power models are motivated and elaborated. The verification of the resulting parameterised models confirms the new concept in a surprising huge design space. The resulting models enable a relatively high accuracy at a low modeling effort. Moreover, it can be shown that the elaborated models can be reused for other implementations of the same arithmetic but using differently implemented and differently placed basic-cells without significant loss in accuracy. With an exemplary investigation of a model for a bit serial non-linear filter, it can be shown that the concept can be generally applied to other structures. The error of the models compared to power simulations, which require a dramatically larger computational effort, was quantified to be better than 10% for all investigated macro types.","abstract_html":"With the continuous exponential growth in complexity and the increasing performance potential of highly integrated CMOS circuits, the power dissipation of such circuits has become one of the most serious design problems. This is not limited to obvious applications, such as hand-held and battery-operated systems or general-purpose-processor based systems, which suffer from a well known, continuously increasing technological challenge due to the energy supply and removal. As well in less obvious applications the power dissipation is often a decisive cost factor. Thus, the power dissipation can have a dramatic influence on the commercial success or can even decide on the realisation of a product due to the necessary choice of an expensive package with a low thermal resistance. Therewith the power dissipation is one of the most important specification parameter which has to be carefully examined during the whole design process and which in case of need has to be minimised in iterative design cycles. With the improvements of simulation techniques today's CAD-tools combine accurate power dissipation values at the physical design level with an acceptable computational effort. But there is a serious lack of concepts for sufficiently accurate power estimation at low computational effort to support the design process on higher system levels. On the other hand the estimation of other parameters, such as the maximum throughput rate and particularly the silicon area is quite simple and is sufficiently well controlled. Therefore, a new concept for power modeling is elaborated and verified in the presented work. Especially for power critical system components in the area of high throughput digital signal processing a physically oriented design flow ensures a highly efficient implementation meeting technological requirements. Therefore, the proposed modeling methodology especially focuses on the constraints and requirements that apply to the power estimation of such highly optimised CMOS-implementations. Based on the structure of the circuit and on the average energy consumptions of the used basic-cells, quite simple arithmetic power models are elaborated which are refined with correction functions. These functions phenomenologically approximate the internal switching activity as a function of the switching activity of the input signals. For the example of transversal filters starting with simple direct form filters, based on atomic components (such as adders and multipliers) to highly optimised filters, power models are motivated and elaborated. The verification of the resulting parameterised models confirms the new concept in a surprising huge design space. The resulting models enable a relatively high accuracy at a low modeling effort. Moreover, it can be shown that the elaborated models can be reused for other implementations of the same arithmetic but using differently implemented and differently placed basic-cells without significant loss in accuracy. With an exemplary investigation of a model for a bit serial non-linear filter, it can be shown that the concept can be generally applied to other structures. The error of the models compared to power simulations, which require a dramatically larger computational effort, was quantified to be better than 10% for all investigated macro types.","abstract_has_math":false,"creators":["Henning, Christiane"],"institution":"Publikationsserver der RWTH Aachen University","degree_name":null,"degree_level":null,"degree_discipline":null,"degree_department":null,"school":null,"contributors":["Noll, Tobias G."],"advisors":[],"committee_chairs":[],"committee_members":[],"year":2002,"date_issued":"2002","date_published":"2002","updated_at":"2026-07-30T19:43:10Z","subjects":["info:eu-repo/classification/ddc/620","Ingenieurwissenschaften"],"languages":["ger"],"rights":["info:eu-repo/semantics/openAccess"],"rights_urls":[],"identifier_entries":[{"key":"dc:identifier","label":"Identifier","values":["https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123065%22"],"render_values":[{"text":"https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123065%22","href":"https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123065%22","code":true}]}]},"links":{"outbound_url":"https://publications.rwth-aachen.de/record/61396","outbound_label":"Repository record","outbound_source":"dc:identifier"},"metadata_groups":[{"id":"people","label":"People","entries":[{"key":"dc:contributor","label":"Contributor","values":["Noll, Tobias G."]},{"key":"dc:creator","label":"Author","values":["Henning, Christiane"]}]},{"id":"academic_context","label":"Academic Context","entries":[{"key":"dc:coverage","label":"Dc Coverage","values":["DE"]},{"key":"dc:date","label":"Dc Date","values":["2002"]},{"key":"dc:publisher","label":"Institution","values":["Publikationsserver der RWTH Aachen University"]},{"key":"dc:relation","label":"Dc Relation","values":["info:eu-repo/semantics/altIdentifier/urn/urn:nbn:de:hbz:82-opus-5882","info:eu-repo/semantics/altIdentifier/doi/10.18154/RWTH-CONV-123065"]},{"key":"dc:type","label":"Dc Type","values":["info:eu-repo/semantics/doctoralThesis","info:eu-repo/semantics/publishedVersion"]}]},{"id":"subjects_keywords","label":"Subjects and Keywords","entries":[{"key":"dc:subject","label":"Dc Subject","values":["info:eu-repo/classification/ddc/620","Ingenieurwissenschaften"]}]},{"id":"language_rights","label":"Language and Rights","entries":[{"key":"dc:language","label":"Dc Language","values":["ger"]},{"key":"dc:rights","label":"Dc Rights","values":["info:eu-repo/semantics/openAccess"]}]},{"id":"identifiers","label":"Identifiers","entries":[{"key":"dc:identifier","label":"Identifier","values":["https://publications.rwth-aachen.de/record/61396","https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123065%22"]}]},{"id":"additional","label":"Additional Metadata","entries":[{"key":"dc:description","label":"Description","values":["With the continuous exponential growth in complexity and the increasing performance potential of highly integrated CMOS circuits, the power dissipation of such circuits has become one of the most serious design problems. This is not limited to obvious applications, such as hand-held and battery-operated systems or general-purpose-processor based systems, which suffer from a well known, continuously increasing technological challenge due to the energy supply and removal. As well in less obvious applications the power dissipation is often a decisive cost factor. Thus, the power dissipation can have a dramatic influence on the commercial success or can even decide on the realisation of a product due to the necessary choice of an expensive package with a low thermal resistance. Therewith the power dissipation is one of the most important specification parameter which has to be carefully examined during the whole design process and which in case of need has to be minimised in iterative design cycles. With the improvements of simulation techniques today's CAD-tools combine accurate power dissipation values at the physical design level with an acceptable computational effort. But there is a serious lack of concepts for sufficiently accurate power estimation at low computational effort to support the design process on higher system levels. On the other hand the estimation of other parameters, such as the maximum throughput rate and particularly the silicon area is quite simple and is sufficiently well controlled. Therefore, a new concept for power modeling is elaborated and verified in the presented work. Especially for power critical system components in the area of high throughput digital signal processing a physically oriented design flow ensures a highly efficient implementation meeting technological requirements. Therefore, the proposed modeling methodology especially focuses on the constraints and requirements that apply to the power estimation of such highly optimised CMOS-implementations. Based on the structure of the circuit and on the average energy consumptions of the used basic-cells, quite simple arithmetic power models are elaborated which are refined with correction functions. These functions phenomenologically approximate the internal switching activity as a function of the switching activity of the input signals. For the example of transversal filters starting with simple direct form filters, based on atomic components (such as adders and multipliers) to highly optimised filters, power models are motivated and elaborated. The verification of the resulting parameterised models confirms the new concept in a surprising huge design space. The resulting models enable a relatively high accuracy at a low modeling effort. Moreover, it can be shown that the elaborated models can be reused for other implementations of the same arithmetic but using differently implemented and differently placed basic-cells without significant loss in accuracy. With an exemplary investigation of a model for a bit serial non-linear filter, it can be shown that the concept can be generally applied to other structures. The error of the models compared to power simulations, which require a dramatically larger computational effort, was quantified to be better than 10% for all investigated macro types."]},{"key":"dc:source","label":"Dc Source","values":["Aachen : Publikationsserver der RWTH Aachen University VI, 100 S. : Ill., graph. Darst. (2002). doi:10.18154/RWTH-CONV-123065 = Aachen, Techn. Hochsch., Diss., 2002"]},{"key":"dc:title","label":"Title","values":["Verlustleistungs-Modellierung exemplarischer Schlüsselkomponenten der hochratigen digitalen Signalverarbeitung"]}]}],"canonical_facts":{"dc:contributor":["Noll, Tobias G."],"dc:coverage":["DE"],"dc:creator":["Henning, Christiane"],"dc:date":["2002"],"dc:description":["With the continuous exponential growth in complexity and the increasing performance potential of highly integrated CMOS circuits, the power dissipation of such circuits has become one of the most serious design problems. This is not limited to obvious applications, such as hand-held and battery-operated systems or general-purpose-processor based systems, which suffer from a well known, continuously increasing technological challenge due to the energy supply and removal. As well in less obvious applications the power dissipation is often a decisive cost factor. Thus, the power dissipation can have a dramatic influence on the commercial success or can even decide on the realisation of a product due to the necessary choice of an expensive package with a low thermal resistance. Therewith the power dissipation is one of the most important specification parameter which has to be carefully examined during the whole design process and which in case of need has to be minimised in iterative design cycles. With the improvements of simulation techniques today's CAD-tools combine accurate power dissipation values at the physical design level with an acceptable computational effort. But there is a serious lack of concepts for sufficiently accurate power estimation at low computational effort to support the design process on higher system levels. On the other hand the estimation of other parameters, such as the maximum throughput rate and particularly the silicon area is quite simple and is sufficiently well controlled. Therefore, a new concept for power modeling is elaborated and verified in the presented work. Especially for power critical system components in the area of high throughput digital signal processing a physically oriented design flow ensures a highly efficient implementation meeting technological requirements. Therefore, the proposed modeling methodology especially focuses on the constraints and requirements that apply to the power estimation of such highly optimised CMOS-implementations. Based on the structure of the circuit and on the average energy consumptions of the used basic-cells, quite simple arithmetic power models are elaborated which are refined with correction functions. These functions phenomenologically approximate the internal switching activity as a function of the switching activity of the input signals. For the example of transversal filters starting with simple direct form filters, based on atomic components (such as adders and multipliers) to highly optimised filters, power models are motivated and elaborated. The verification of the resulting parameterised models confirms the new concept in a surprising huge design space. The resulting models enable a relatively high accuracy at a low modeling effort. Moreover, it can be shown that the elaborated models can be reused for other implementations of the same arithmetic but using differently implemented and differently placed basic-cells without significant loss in accuracy. With an exemplary investigation of a model for a bit serial non-linear filter, it can be shown that the concept can be generally applied to other structures. The error of the models compared to power simulations, which require a dramatically larger computational effort, was quantified to be better than 10% for all investigated macro types."],"dc:identifier":["https://publications.rwth-aachen.de/record/61396","https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-123065%22"],"dc:language":["ger"],"dc:publisher":["Publikationsserver der RWTH Aachen University"],"dc:relation":["info:eu-repo/semantics/altIdentifier/urn/urn:nbn:de:hbz:82-opus-5882","info:eu-repo/semantics/altIdentifier/doi/10.18154/RWTH-CONV-123065"],"dc:rights":["info:eu-repo/semantics/openAccess"],"dc:source":["Aachen : Publikationsserver der RWTH Aachen University VI, 100 S. : Ill., graph. Darst. (2002). doi:10.18154/RWTH-CONV-123065 = Aachen, Techn. Hochsch., Diss., 2002"],"dc:subject":["info:eu-repo/classification/ddc/620","Ingenieurwissenschaften"],"dc:title":["Verlustleistungs-Modellierung exemplarischer Schlüsselkomponenten der hochratigen digitalen Signalverarbeitung"],"dc:type":["info:eu-repo/semantics/doctoralThesis","info:eu-repo/semantics/publishedVersion"]},"updated_at":"2026-07-30T19:43:10Z"}