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Showing 1 to 8 of 8 for “"transition fault"”.

  1. Experimental Study of Scan Based Transition Fault Testing Techniques

    … test for such delay-inducing defects, scan-based transition fault testing techniques are being implemented. There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed …

    vt Repository record for Experimental Study of Scan Based Transition Fault Testing Techniques (opens in a new tab)

  2. High Quality Transition and Small Delay Fault ATPG

    … selection and generating tests for small delay faults is an important issue in the delay fault area. A novel technique for generating effective vectors for delay defects is the first issue that we have presented in the thesis. The test set achieves high path delay fault coverage to capture …

    vt Repository record for High Quality Transition and Small Delay Fault ATPG (opens in a new tab)

  3. TENOR: an ATPG for transition faults in combinational circuits

    Delay fault testing of high speed VLSI circuits is becoming increasingly important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The …

    vt Repository record for TENOR: an ATPG for transition faults in combinational circuits (opens in a new tab)

  4. Late Cenozoic Exhumation in a Transpressional Setting: Fairweather Range, Alaska

    … of the Yakutat terrane as margin-parallel motion transitions to subduction. Recent studies have shown that deformation in the St. Elias orogen, at the northern end of the terrane, accommodates a large portion of convergence, but deformation at the eastern and southern margins remains more poorly …

    vt Repository record for Late Cenozoic Exhumation in a Transpressional Setting: Fairweather Range, Alaska (opens in a new tab)

  5. VALIDATION OF CIRCUIT TIMING BEHAVIOR IN THE PRESENCE OF DELAY DEFECTS AND NBTI AGING

    … and interconnect. The traditional stuck-at, and transition fault model are not appropriate to model such defects. They must be tested appropriately by targeting critical paths in the circuit. Furthermore, reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot carrier …

    siu-theses Repository record for VALIDATION OF CIRCUIT TIMING BEHAVIOR IN THE PRESENCE OF DELAY DEFECTS AND NBTI AGING (opens in a new tab)

  6. ATPG and DFT Algorithms for Delay Fault Testing

    … and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based …

    vt Repository record for ATPG and DFT Algorithms for Delay Fault Testing (opens in a new tab)

  7. Brittle-viscous deformation cycles at the base of the seismogenic zone in the continental crust

    … at different scales of a brittle-viscous fault zone active at the base of the seismogenic crust. Object of analysis are samples from the sinistral strike-slip fault zone BFZ045 from Olkiluoto (SW Finland), located at the site of a deep geological repository for nuclear waste. Combined …

    plymouth Repository record for Brittle-viscous deformation cycles at the base of the seismogenic zone in the continental crust (opens in a new tab)