Global ETD Search
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Showing 1 to 6 of 6 for “"timing aware"”.
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Defending Real-Time Systems through Timing-Aware Designs
… systems. The first work introduces a novel timing aware defense strategy for the CAN bus that utilizes TrustZone on state-of-the-art ARMv8-M microcontrollers. The second reduces the runtime cost of control-flow integrity (CFI), a popular system security defense technique, by correctly …
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Timing-Aware Automatic Floorplanning of Partially Reconfigurable Designs for Accelerating FPGA Productivity
… of debug logic. Automatic generation of a timing-driven floorplan for a partially reconfigurable design aims to remove the need for implementation iterations to meet all constraints. Floorplan speculation may anticipate small changes to a design. Although PATIS supports incremental design, …
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Automatic Instantiation and Timing-Aware Placement of Bus Macros for Partially Reconfigurable FPGA Designs
… the existing implementation flows facilitate timing closure late in the design cycle by reusing the layout of unmodified blocks, dynamic modular design accelerates implementation by achieving timing closure for each block independently. A complete re-implementation is still rapid as the design …
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Delay Testing in Nanoscale Technology under Process Variations
… model, which better describes the circuit timing behavior under variations, is not yet sufficiently investigated and employed by existing testing methodologies. This thesis work proposes Opt-KLPG and MIRID, which can be utilized by a statistical delay testing flow. Opt-KLPG—a K Longest …
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Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
… proposed a novel synthesis paradigm to achieve timing-closure called Timing-Aware CUt Enumeration (TACUE). In TACUE, optimization is conducted through three aspects: First, we propose a new divide-and-conquer strategy that generates multiple sub-cuts on the critical parts of the circuit. …
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Opacity Verification and Fault Diagnosis in the Framework of Switching Output Automata
… models capture event sequences but lack native timing semantics, while dense-time formalisms such as timed automata face undecidability or prohibitive complexity for verification tasks involving both timing constraints and partial observability. This dissertation introduces the Switching Output …