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Showing 1 to 8 of 8 for “"time multiplexing"”.

  1. Architectural Support for Effective Data Compression In Irregular Applications

    … implementation leverages dataflow execution and time-multiplexing to implement programmability cheaply. We evaluate SpZip on a simulated multicore system running a broad set of graph and linear algebra algorithms. SpZip outperforms prior state-of-the art software-only (hardware-accelerated) …

    mit Repository record for Architectural Support for Effective Data Compression In Irregular Applications (opens in a new tab)

  2. An embedded system supporting dynamic partial reconfiguration of hardware resources for morphological image processing

    … hardware configuration of silicon pieces at runtime. DPR allows regions of the FPGA to be reprogrammed with new functionality while applications are still running in the remainder of the device. The main aim of this thesis is to design an embedded system for morphological image processing by …

    njit Repository record for An embedded system supporting dynamic partial reconfiguration of hardware resources for morphological image processing (opens in a new tab)

  3. New Tools for Real-Time Study of Embryonic Development

    … embryonic development <em>in vivo</em> in real-time at single-cell and single-molecule resolutions. In this dissertation, we have developed a wide range of innovative tools for real-time study of embryonic development. These new tools include biocompatible and photostable plasmonic gold (Au) and …

    odu Repository record for New Tools for Real-Time Study of Embryonic Development (opens in a new tab)

  4. Throughput Constrained and Area Optimized Dataflow Synthesis for FPGAs

    … more area-efficient circuit modules or by time-multiplexing faster, larger circuit modules, while meeting the throughput constraint. The results of this work show that the combined approach can generate on average 43% smaller hardware than possible when a single technique (resource sharing …

    byu Repository record for Throughput Constrained and Area Optimized Dataflow Synthesis for FPGAs (opens in a new tab)

  5. Hybrid Opto-Electronic Processing Systems for Integer Multiplication

    … multiplication results by incorporating a time-multiplexing technique for the first time. This level of accuracy and bit-precision improvement has already made the encoding method itself promising, given that only 5 and 25 resolvable levels are required for the multi-level SLM and the …

    cambridge Repository record for Hybrid Opto-Electronic Processing Systems for Integer Multiplication (opens in a new tab)

  6. Advanced Computational Holography for Perceptual Enhancement and Application in HUDs

    … direct expansion, reducing the computational time by 39% for a 3×3 configuration and 59% for a 5×5 subpixel lattice. Furthermore, the zero-order contribution is analysed and effectively suppressed. In parallel, the kernel shape is investigated to capture the physical characteristics of liquid …

    cambridge Repository record for Advanced Computational Holography for Perceptual Enhancement and Application in HUDs (opens in a new tab)

  7. Nonlinear Dynamics and Chaos in Systems with Time-Varying Delay

    Systeme mit Zeitverzögerung sind dadurch charakterisiert, dass deren zukünftige Entwicklung durch den Zustand zum aktuellen Zeitpunkt nicht eindeutig festgelegt ist. Die Historie des Zustands muss in einem Zeitraum bekannt sein, dessen Länge Totzeit genannt wird und die Gedächtnislänge festlegt. In …

    qucosa-diss