Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 21 for “"time interleaved"”.
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A time-interleaved Zero-Crossing-Based analog-to-digital converter
… issues. This research applies ZCB techniques to Time Interleaved ADCs (TIADC). Mismatch between the individual ADCs, or channels, that make up the TIADC degrade its accuracy and is a fundamental design challenge. This research addresses the mismatch issue by investigating new circuit techniques …
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Calibration of sampling clock skew in high-speed, high-resolution time-interleaved ADCs
… rates of ADCs in a power efficient manner, time-interleaving is an essential technique, whereby N ADC channels, each operating at a sampling frequency of fs, are used to achieve an effective conversion rate of N - fs. While time-interleaving enables higher conversion rates in a given …
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Design and implementation of generalized topologies of time-interleaved variable bandpass Σ−Δ modulators
… and digital-to-analog generalized time-interleaved variable bandpass sigma-delta modulators are designed, analysed, evaluated and implemented that are suitable for high performance data conversion for a broad-spectrum of applications. These generalized time-interleaved variable …
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Post Conversion Correction of Non-Linear Mismatches for Time Interleaved Analog-to-Digital Converters
Time Interleaved Analog-to-Digital Converters (TI-ADCs) utilize an architecture which enables conversion rates well beyond the capabilities of a single converter while preserving most or all of the other performance characteristics of the converters on which said architecture is based. Most of the …
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Signal reconstruction in distributed sampling systems with application to time-interleaved A/D converters
High-speed distributed sampling systems, such as time-interleaved analog-to-digital converters, are becoming increasing popular for many modern applications. Calibration is a serious challenge in the design of such systems. Indeed, component variations and layout constraints lead to gain mismatches …
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Timing offset and quantization error trade-off in interleaved multi-channel measurements
Time-interleaved analog-to-digital converters (ADCs) are traditionally designed with equal quantization granularity in each channel and uniform sampling offsets. Recent work suggests that it is often possible to achieve a better signal-to-quantization noise ratio (SQNR) with different quantization …
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Techniques for low-power high-performance ADCs
… efficiency. The second design is a high speed time-interleaved (TI) SAR ADC with background timing-skew calibration. A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency. SAR ADCs are used for each channel to make good use of …
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A Software Defined Ultra Wideband Transceiver Testbed for Communications, Ranging, or Imaging
… dissertation outlines the development of the Time-Interleaved Analog to Digital Converter array which served as the core of the testbed, along with a comprehensive theoretical and simulation-based analysis on the effects of Analog to Digital Converter mismatches in a Time-Interleaved Sampling …
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Design, simulation, and implementation of a digital quadrature demodulator for a stepped frequency radar
… phase of the intermediate frequency signal of a time-interleaved dual-channel heterodyne radar receiver. A demodulator model is developed from a survey of the relevant literature, paying particular attention to errors introduced in sampling. Simulations predict the demodulator performance in the …
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An FPGA Software-Defined Ultra Wideband Transceiver
… sampling frequency of up to 8 G-samples/s using time interleaved sampling with eight 1-GHz ADCs. The system is also capable of transmitting UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA design used to capture and export data from the eight ADCs is …
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Partial Symbol Detection Based Energy-Efficient Receiver for Short-Reach Optical Communication
… receiver features TIA and CTLE followed by 8-way time-interleaved signal processing unit that corrects pre- and post-cursor ISI. The inverter-based TIA topology provides 70dB gain, 29.65GHz bandwidth, and 1.594μA input-referred noise.
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Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC
… to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, …
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Energy-efficient analog-to-digital conversion for ultra-wideband radio
… to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network …
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An 8 GHz Ultra Wideband Transceiver Testbed
… The receiver uses eight 1 GHz ADCs to perform time interleaved sampling at an aggregate rate of 8 Gsamples/s. The high sampling rates present extraordinary demands on the down-conversion resources. Samples are captured by the high-speed ADC and processed using a Xilinx Virtex-II Pro (XC2VP70) …
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Successive-approximation-register based quantizer design for high-speed delta-sigma modulators
… This thesis focuses on the design of high-speed time-interleaved multi-bit successive-approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs …
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Estimation and calibration algorithms for distributed sampling systems
… the physical layout; while in other cases like time-interleaved analog-to-digital converters, additional components are added to increase the sampling rate. Although distributing the sampling load across multiple channels can provide large benefits in terms of speed, power, and resolution, a …
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Low-power high-performance SAR ADC design with digital calibration techniques
… The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB …
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Design Techniques for High-Performance SAR A/D Converters
… technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique …
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Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
… reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated …
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