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Showing 1 to 6 of 6 for “"temporal safety"”.

  1. Efficient spatial and temporal safety for microcontrollers and application-class processors

    … research in reducing the overheads for achieving temporal safety with CHERI. CHERI offers a contemporary cross-architecture description of capabilities. The initial design was previously carried out in a single MIPS processor. Based on its success in this context, this thesis investigates the …

    cambridge Repository record for Efficient spatial and temporal safety for microcontrollers and application-class processors (opens in a new tab)

  2. Memory safety with CHERI capabilities: security analysis, language interpreters, and heap temporal safety

    … protection model that facilitates memory safety and fine-grained compartmentalization for software. The architecture has reached a mature state and been integrated into Arm’s industrial-scale Morello system-on-chip, a large corpus of software has been adapted to support CHERI, and prior …

    cambridge Repository record for Memory safety with CHERI capabilities: security analysis, language interpreters, and heap temporal safety (opens in a new tab)

  3. Safety-driven software design and engineering in medical cyber-physical-human systems

    … addresses the questions of how to ensure safety in medical Cyber-Physical-Human System (CPHS) development from various perspectives including (1) System Design for Networked Medical CPHS, (2) Safety-driven Requirement and Software Traceability, and (3) System and Human Behavior Modeling. …

    uiuc Repository record for Safety-driven software design and engineering in medical cyber-physical-human systems (opens in a new tab)

  4. Capability Memory Protection for Embedded Systems

    … embedded systems, to address existing memory safety and task isolation problems as well as providing new means to design a secure and scalable real-time system. In addition, this dissertation looks into how practical and high-performance temporal memory safety can be achieved under a …

    cambridge Repository record for Capability Memory Protection for Embedded Systems (opens in a new tab)

  5. CheriOS: Designing an untrusted single-address-space capability operating system utilising capability hardware and a minimal hypervisor

    … for and run on CheriOS offer full memory safety, both spatial and temporal, enforced control flow integrity between compartments and protection against common vulnerabilities such as buffer overflows, code injection and Return-Oriented-Programming attacks. I achieve this by designing a new …

    cambridge Repository record for CheriOS: Designing an untrusted single-address-space capability operating system utilising capability hardware and a minimal hypervisor (opens in a new tab)

  6. Formalizing operator task analysis

    … severe or even fatal consequences especially in safety critical systems. A generalized methodology that can allow modeling and analyzing the interactions between computer systems and human operators where the operators are allowed to deviate from their prescribed behaviors will provide a formal …

    uiuc Repository record for Formalizing operator task analysis (opens in a new tab)