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Showing 1 to 5 of 5 for “"temporal memory safety"”.

  1. TRUSTED RUNTIME ENVIRONMENTS FOR EMBEDDED SYSTEMS: FROM MEMORY PROTECTION TO SECURE VIRTUALIZATION

    … constrained by limited computational and memory resources. This thesis addresses these challenges by proposing lightweight, scalable mechanisms for runtime memory protection and secure execution, with an emphasis on minimizing device overhead through remote verification. To strengthen …

    milano Repository record for TRUSTED RUNTIME ENVIRONMENTS FOR EMBEDDED SYSTEMS: FROM MEMORY PROTECTION TO SECURE VIRTUALIZATION (opens in a new tab)

  2. Asynchronous hardware-enforced memory safety

    Memory corruption attacks, such as buffer overflow attacks, have been threatening software security for more than three decades. Despite tremendous efforts by developers and researchers to prevent programs written in memory-unsafe language (e.g., C/C++) from memory errors (the root cause of memory

    uiuc Repository record for Asynchronous hardware-enforced memory safety (opens in a new tab)

  3. Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns

    … of three approaches using data race bugs, memory safety bugs, and permission check bugs, respectively. First, we leverage the commodity hardware transactional memory (HTM) selectively to use the dynamic data race detector only if necessary, thereby reducing the overhead from 11.68x to …

    vt Repository record for Designing Practical Software Bug Detectors Using Commodity Hardware and Common Programming Patterns (opens in a new tab)

  4. Capability Memory Protection for Embedded Systems

    … embedded systems, to address existing memory safety and task isolation problems as well as providing new means to design a secure and scalable real-time system. In addition, this dissertation looks into how practical and high-performance temporal memory safety can be achieved under a …

    cambridge Repository record for Capability Memory Protection for Embedded Systems (opens in a new tab)

  5. Toward transient-execution attack mitigations on CHERI

    … capabilities that help to tackle spatial and temporal memory safety issues. However, the CHERI ISA has not been designed with transient-execution vulnerabilities in mind. In order to satisfy performance requirements, CHERI implementations employ out-of-order and speculative execution …

    cambridge Repository record for Toward transient-execution attack mitigations on CHERI (opens in a new tab)