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Showing 1 to 2 of 2 for “"tag cache"”.
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High-performance memory safety - Optimizing the CHERI capability machine
… to increased memory bandwidth requirements and cache pressure when using CHERI capabilities in place of conventional 64-bit pointers. In order to mitigate this cost, I present two new 128-bit CHERI capability formats, using different compression techniques, while preserving C-language …
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Architectural techniques to extend multi-core performance scaling
… the die-stacked DRAM is expected to be used as a cache, storing any part of the tag in the DRAM itself erodes the bandwidth advantage of die-stacking. As such, the on-die space overhead of the large DRAM cache's tag is a concern. A well-known compromise is to employ a small on-die tag cache …