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Showing 1 to 5 of 5 for “"system-level electrostatic discharge (ESD)"”.

  1. Enhanced modeling methodology for system-level electrostatic discharge simulation

    To enable accurate system-level electrostatic discharge (ESD) simulation, models for the equipment under test, the ESD source, and the environment are required. This work presents advanced modeling methods for the ESD source, the victim IC, and other on-board components, most notably the transient …

    uiuc Repository record for Enhanced modeling methodology for system-level electrostatic discharge simulation (opens in a new tab)

  2. Characterization and modeling of ESD events and near-field scanning calibration structures

    … that cover, two major topics. The first topic, system-level electrostatic discharge (ESD), is discussed over the course of two papers. The second topic, a calibration structure for near-field scanning probe calibration application, is discussed in the last paper. In the first paper, …

    must-thes Repository record for Characterization and modeling of ESD events and near-field scanning calibration structures (opens in a new tab)

  3. Failures caused by supply fluctuations during system-level ESD

    It is necessary to design robust electronic systems against system-level electrostatic discharge (ESD). In additional to withstanding ESD without hard failures (permanent damage), it is important that the system is robust against soft failures (recoverable loss of function or data), which can be …

    uiuc Repository record for Failures caused by supply fluctuations during system-level ESD (opens in a new tab)

  4. Understanding, modeling, and mitigating system-level ESD in integrated circuits

    … several studies regarding the effects of system-level electrostatic discharge (ESD) and how to model and mitigate them. The topics in this dissertation fall into two broad categories: modeling pieces of a system-level ESD test setup and phenomenological studies. Simulation is an important …

    uiuc Repository record for Understanding, modeling, and mitigating system-level ESD in integrated circuits (opens in a new tab)

  5. Logic upset induced by substrate current during power-on ESD

    … possible soft failure mechanism during power-on electrostatic discharge (ESD). For contact discharge into a test chip mounted on a board, logic upsets can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. This type of upset often …

    uiuc Repository record for Logic upset induced by substrate current during power-on ESD (opens in a new tab)