Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 17 of 17 for “"stuck-at faults"”.
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TENOR: an ATPG for transition faults in combinational circuits
… important. This thesis presents an Automatic Test Pattern Generator (ATPG), called TENOR, for transition faults. Transition faults are a special case of gate delay faults. Test generation is based on the FAN algorithm. The approach taken in this thesis is to map a transition fault into …
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On fault tolerance of hardware samplers
In this research, we evaluate the robustness of hardware samplers to hardware faults. This study was motivated by our observation that several applications use sampling as a primitive and that sampling itself is an approximate method for computation. As such, it might be possible to lower energy …
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Toward high-level synthesis of reliable circuits through low-cost modulo shadow datapaths
With transistor dimensions shrinking to the atomic scale, a plethora of new reliability problems presents a barrier to continued Moore’s law scaling. Traditional modular redundancy techniques with 2x and 3x area cost eliminate the area reduction benefits of such scaling. In this study, we take a …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
Fault collapsing, test generation, and fault simulation were traditionally developed at the gate-level based on the stuck-at fault model. However, with the advent of VLSI MOS technology, this fault model is not applicable. In order to reduce the number of faults which need to be considered in the …
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An investigation of sensitization conditions and test effectiveness for CMOS faults
… of conventional test methods based on line stuck-at faults in testing CMOS circuits and has proposed new test methods. In this research, the effectiveness of propagation delay testing for open and short faults and supply current monitoring for short faults is investigated. Representative …
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Implementation of a testing and initialization algorithm for the generalized tree structure
… implementing a detection algorithm for multiple stuck-at faults occurring within the structure of a generalized tree using, as the testing machines, a set of generalized sequential trees. It is shown that the testing machine can be implemented on a set of trees of the same depth as that of the …
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On the generation of test patterns for combinational circuits
In this thesis, methods of identification of redundant faults and test pattern compaction are presented. The aim of the research is to improve an existing test pattern generator ATALANTA by incorporating methods for identification of redundant faults and test compaction. The faults are modeled as …
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Diagnostic test set evaluation and enhancement
… diagnosis topics, namely diagnostic fault simulation and diagnostic test pattern generation. First, a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient is described. The simulator represents indistinguishable classes of faults as memory …
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Fault detection and location in modular trees
The problem of fault detection and location in modular tree structures are considered in this thesis. The fault set is restricted to stuck-at-faults in the discussion of the fault location problem. Short circuit faults and broken and short circuit faults are considered in the discussion of the …
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Experimental Study of Scan Based Transition Fault Testing Techniques
… There exist organized techniques to generate test patterns for the transition fault model and the two popular methods being used are Broad-side delay test (Launch-from-capture) and Skewed load delay test (Launch-from-shift). Each method has its own drawbacks and many practical issues are …
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Developing a multi-level fault injection environment
… interference can cause internal state of the system to change, which might cause errors to the system with non-negligible probability. Such errors are termed "soft errors". Bit flips in the design are good way to model these soft-errors. These bit-flips due to soft errors are random …
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A formal model for behavioral test generation
A formal behavioral test generation algorithm, called the B-algorithm, is presented together with a behavioral VHDL model and a realistic behavioral fault model. Using the behavioral VHDL model, a behavioral VHDL circuit description is represented as a set of equivalent process Statements and …
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Techniques for Seed Computation and Testability Enhancement for Logic Built-In Self Test
With the increase of device complexity and test-data volume required to guarantee adequate defect coverage, external testing is becoming increasingly difficult and expensive. Logic Built-in Self Test (LBIST) is a viable alternative test strategy as it helps reduce dependence on an elaborate …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
In this work, at first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for …
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Low-cost error detection through high-level synthesis
… resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide …
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Static Learning for Problems in VLSI Test and Verification
Static learning in the form of logic implications captures Boolean relationships between various gates in a circuit. In the past, logic implications have been applied in several areas of electronic design automation (EDA) including: test-pattern-generation, logic and fault simulation, fault …
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Robust and reliable hardware accelerator design through high-level synthesis
… resulted in a variety of reliability and validation challenges including logic bugs, hot spots, wear-out, and soft errors. To make matters worse, as we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide …