Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 26 for “"strained-Si"”.
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Transport in thin-body MOSFETs fabricated in strained Si and strained Si/SiGe heterostructures on insulator
… such as strain engineering, with non-classical MOS device architectures, such as ultra-thin body or multiple-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future CMOS technology nodes. …
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SiGe-on-insulator and strained-Si-on-insulator for strained-Si CMOS and nanocrystalline-Ge waveguides
SiGe-on-insulator (SGOI) and strained-Si-on-insulator (SSOI) substrates combine both the benefits of a high-quality, monocrystalline SiGe or strained-Si surface layer with the advantages of an insulating substrate. In particular, many electronic and photonic devices are greatly enhanced by the use …
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Strained-Si technology for RF power LDMOSFET
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.
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Electronic Defect Characterization of Strained-Si/SiGe/Si Heterostructure
North Carolina State University Theses Materials Science and Engineering.
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Physical studies of strained Si/SiGe heterostructures : from virtual substrates to nanodevices
… the past two decades, the decrease in intrinsic delay of MOSFETs has been driven by the scaling of the device dimensions. The performance improvement has relied mostly in the increase of source velocity with gate scaling, while the transport properties of the channel have remained constant, …
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High mobility strained Si/SiGe heterostructure MOSFETs : channel engineering and virtual substrate optimization
High quality relaxed silicon-germanium graded buffers are an important platform for monolithic integration of high speed heterostructure field-effect transistors and III-V-based optoelectronics onto silicon substrates. In this thesis, dislocation dynamics in compositionally graded SiGe layers are …
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MOSFET channel engineering using strained Si and strained Ge grown on SiGe virtual substrates
… of scaling in very-large-scale-integrated (VLSI) circuits decreases, the use of alternative channel materials such as germanium and strained silicon ([epsilon]-Si) is increasingly being considered as a method for improving the performance of MOSFETs. While [epsilon]-Si grown on relaxed …
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Investigation of mechanisms and influencing processing factors on mobility enhancement in strained Si n-MOSFETs
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
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Investigation of the electron transport and electrostatics of nanoscale strained Si/Si/Ge heterostructure MOSFETs
This thesis presents work aimed at investigating the possible benefit of strained-Si/SiGe heterostructure MOSFETs designed for nanoscale (sub-50-nm) gate lengths with the aid of device fabrication and electrical measurements combined with computer simulation. MOSFET devices fabricated on bulk-Si …
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Silicon-Germanium interdiffusion and its impacts on enhanced mobility MOSFETs
… metal-oxide-semiconductor field-effect transistors (MOSFETs) scale, strained Si and SiGe technology have received more attention as a means of enhancing performance via improved carrier mobility. One of the biggest challenges for strained Si and SiGe technology is Si-Ge interdiffusion during …
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Fundamental limits of the switching abruptness of tunneling transistors
The tunneling field-effect transistor (TFET) is one of the most promising candidates for future low-power electronics because of its potential to achieve a subthreshold swing less than the 60 mV/decade thermal limit at room temperature. It can surpass this limit because the turn-on of tunneling …
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Gate-all-around silicon nanowire MOSFETs : top-down fabrication and transport enhancement techniques
… 15 nm gate lengths is extremely challenging using a planar device architecture due to the stringent criteria required for the transistor switching. The top-down fabricated, gate-all-around architecture with a Si nanowire channel is a promising candidate for future technology generations. The …
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Electron transport in ultrathin-body fully depleted n-MOSFETS fabricated on strained silicon directly on insulator with body thickness ranging from 22nm to 25 nm
… (UTB) n-MOSFETs fabricated on Ge-free 30% strained-Si directly on insulator (SSDOI) is mapped as the body thickness is scaled. Effective mobility and device body thickness were extracted using current-voltage and gate-to-channel capacitance-voltage measurements as well as cross section …
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Raman spectroscopy: from ferroelastic domain identification to strain tuning
This cumulative Habilitation thesis summarizes several examples related to the application of Raman spectroscopy for the investigation of coupling phenomena induced by epitaxially, mechanically or piezoeletrically applied strain. Methods for quantitative determination of strain by Raman …
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Hole transport in strained SiGe-channel MOSFETs : velocity in scaled devices and mobility under applied mechanical strain
Since the 90 nm CMOS technology node, geometric scaling of CMOS has been supplemented with strain to boost transistor drive current. Future CMOS technology nodes (i.e. beyond the 32 nm node) will require more significant changes to continue improvements in transistor performance. Novel CMOS channel …
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Compressively strained Ge trigate p-MOSFETs
… properties of the material that is being used, silicon (Si). In order to continue performance enhancements, different materials are being studied for the extension of Si CMOS. One of the materials of interest, particularly for p-MOSFETs, is Ge because it has very high intrinsic hole mobility. …
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Impact of uniaxial strain on P-channel 111-V quantum-well field effect transistors
Continuous scaling of Si complementary metal-oxide-semiconductor (CMOS) technology requires a boost in carrier injection velocity. With the benefits of strained Si having been exhausted, n-channel I-V quantum-well field effect transistors (QW-FETs) show promising potential as a post-Si CMOS logic …
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Tensile-strained Germanium via III-V Heterostructures for Emerging Electronic and Photonic Applications
The relentless scaling down of feature dimensions in silicon (Si)-based complementary metal-oxide-semiconductor (CMOS) architectures has been the primary catalyst for the enhancement of technological functionalities within portable electronic systems and computational infrastructures. Concurrently, …
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Prospects of germanium-based MOSFETs and tunnel transistors for low power digital logic
… by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As …
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Templated self-assembly of SiGe quantum dots
This PhD thesis reports on the fabrication and characterization of exact aligned SiGe quantum dot structures. In general, SiGe quantum dots which nucleate via the Stranski-Krastanov growth mode exhibit broad size dispersion and nucleate randomly on the surface. However, to tap the full potential of …
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