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Showing 1 to 1 of 1 for “"stochastic interconnect estimation"”.
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Temperature and Interconnect Aware Unified Physical and High Level Synthesis
… of ASICs with optimal chip temperatures and interconnect delays. Thermal issues are becoming a serious problem in high-performance VLSI circuits, adversely impacting performance, reliability, power consumption, and cooling costs. To address this, we present a temperature-aware behavioral …