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Showing 1 to 6 of 6 for “"split-capacitor"”.

  1. Energy Harvesting IC Design for an Electromagnetic Generator Based on the Split Capacitor Approach

    … The proposed circuit is a synchronous split-capacitor boost converter operating in boundary conduction mode (BCM) to achieve impedance matching and therefore maximum power transferred to the load. The circuit topology combines the rectifier and power stage to reduce power loss of the …

    vt Repository record for Energy Harvesting IC Design for an Electromagnetic Generator Based on the Split Capacitor Approach (opens in a new tab)

  2. Applying mass and energy balances to model series and parallel fan-powered terminal units.

    … These data included two fan motors: permanent split capacitor motors with silicon controlled rectifier control and electronically commutated motors. Fan sizes ranged from approximately 250 to 3500 ft³/min (0.118 to 1.65 m³/s) and motor sizes ranged from one-third to one hp (248.6 to 745.7 W). A …

    baylor Repository record for Applying mass and energy balances to model series and parallel fan-powered terminal units. (opens in a new tab)

  3. A highly digital, reconfigurable and voltage scalable SAR ADC

    … digital-to -analog converter (DAC) in a split capacitor topology with a sub-DAC is used to minimize the DAC power and area. Top plate switches are used to decouple the MSB capacitors as resolution is scaled to avoid parasitic loading of the DAC. The DAC capacitors are laid out in a …

    mit Repository record for A highly digital, reconfigurable and voltage scalable SAR ADC (opens in a new tab)

  4. Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s

    … analyses the circuit limitations of the switched capacitor DAC and the settling problems of the reference voltage associated with a switched capacitor scheme. The switched capacitor DAC is a critical block for overall ADC performance and various trade-offs are weighed up before discussing the …

    cork Repository record for Investigation and design of key circuit blocks in a 10 bit SAR ADC at 100 MS/s (opens in a new tab)

  5. Design of ultra low power analog-to-digital converter for ambulatory EEG recording

    … DAC is utilized to enhance the CMRR. Concepts of split-capacitor array and sub-DAC are combined to reduce the DAC area and power consumption. Charge pumps are used to boost the control voltage of sampling switches. The ADC performs a conversion every 16 clock cycle while being governed by a …

    mit Repository record for Design of ultra low power analog-to-digital converter for ambulatory EEG recording (opens in a new tab)

  6. Topology and Control Investigation of Soft-Switching DC-DC Converters for DC Transformer (DCX) Applications

    … resonant-type EET-DCX with a series resonant capacitor. Following this concept, two specific topologies, hybrid EET-DCX and hybrid RC EET-DCX, are proposed. The main difference between these topologies is that the former adopts a full bridge. In a hybrid RC EET-DCX, a resonant current …

    vt Repository record for Topology and Control Investigation of Soft-Switching DC-DC Converters for DC Transformer (DCX) Applications (opens in a new tab)